Patent US3706130A successfully refreshed from Google Patents.
US3706130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage distribution for integrated circuits
Assignee: Motorola Solutions Inc
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Filing: 1970-07-13
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Granted: 1972-12-19
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Expires: 1990-07-13
Abstract
Abstract A voltage distribution system formed in a monolithic integrated circuit structure and a process for making same. Adjacent P-type and N-type conductivity semiconductor layers form respective portions of separate conductive paths for distributing electrical potentials to semiconductor devices or other components within the same integrated structure. P-type and N-type channels are formed within various portions of the semiconductor layers to complete the conductive paths, and reverse biased junctions electrically isolate the conductive paths and prevent electrical interference between same.
Inventors
- 👤 Walter C Seelbach
- 👤 Kyriakose Lampathakis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:49
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/311; H10W; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
356 words
A process for forming a voltage distribution system to provide conductive paths within a multilayer chip of semiconductor material, the conductive paths consisting of portions of said multilayer chip which are biased in such a manner that no undesirable electrical interference occurs between adjacent portions of the layers of the multilayer chip which are used to distribute voltages, said method comprising: a. providing a substrate of one conductivity type semiconductor material; b. forming a second region of opposite conductivity type semiconductor material adjacent said substrate; c. forming a channel portion withiN said second region of said one conductivity type semiconductor material, said channel portion formed integral with said first region of one conductivity type semiconductor material and adapted to be reverse biased with respect to said second region of semiconductor material so that the electrical potential of said second region does not adversely interact with the electrical potential on said channel portion or the electrical potential on said first region, d. forming a third region of said one conductivity type semiconductor material adjacent said second region and in electrical connection and integral with said channel portion of said one conductivity type within said second region of semiconductor material, said third region being adapted to be reverse biased with respect to said second region so that the electrical potential on said second region does not adversely interact with the electrical potential on said third region, said first and third regions and channel portion all being of said one conductivity type semiconductor material and thereby providing a continuous path for voltage distribution from said first region to the surface of said third region and making available at the surface of said third region an electrical potential, and e. applying electrode means to said first and second regions for applying a voltage to and reverse biasing said first and third regions and said channel portion with respect to said second region, whereby said first, second and third regions and said channel portions are utilized as voltage transmission paths between a DC supply voltage connectable to said electrode means and semiconductor devices and integrated circuits fabricated within said third region.
Claim 2
Dependent Claim
356 words
A process for forming a voltage distribution system to provide conductive paths within a multilayer chip of semiconductor material, the conductive paths consisting of portions of said multilayer chip which are biased in such a manner that no undesirable electrical interference occurs between adjacent portions of the layers of the multilayer chip which are used to distribute voltages, said method comprising: a. providing a substrate of one conductivity type semiconductor material; b. forming a second region of opposite conductivity type semiconductor material adjacent said substrate; c. forming a channel portion withiN said second region of said one conductivity type semiconductor material, said channel portion formed integral with said first region of one conductivity type semiconductor material and adapted to be reverse biased with respect to said second region of semiconductor material so that the electrical potential of said second region does not adversely interact with the electrical potential on said channel portion or the electrical potential on said first region, d. forming a third region of said one conductivity type semiconductor material adjacent said second region and in electrical connection and integral with said channel portion of said one conductivity type within said second region of semiconductor material, said third region being adapted to be reverse biased with respect to said second region so that the electrical potential on said second region does not adversely interact with the electrical potential on said third region, said first and third regions and channel portion all being of said one conductivity type semiconductor material and thereby providing a continuous path for voltage distribution from said first region to the surface of said third region and making available at the surface of said third region an electrical potential, and e. applying electrode means to said first and second regions for applying a voltage to and reverse biasing said first and third regions and said channel portion with respect to said second region, whereby said first, second and third regions and said channel portions are utilized as voltage transmission paths between a DC supply voltage connectable to said electrode means and semiconductor devices and integrated circuits fabricated within said third region.
Claim 3
Dependent Claim
89 words
The process according to claim 1 which further includes: a. forming a second channel portion of said opposite conductivity type semiconductor material wholly within said third region and in electrical contact with said second region, and b. reverse biasing said second channel portion with respect to said third region for providing electrical isolation between said second channel portion and said third region for permitting the distribution of electrical potentials from said second region and through said second channel portion to the surface of a multilayer monolithic integrated circuit structure.
Claim 4
Dependent Claim
172 words
The process according to claim 2 wherein: a. said forming said second region includes epitaxially growing a P-type layer of semiconductor material upon an N-type substrate layer of semiconductor material, b. said forming said channel portion within said second region includes diffusing an N+ channel portion through said P-type layer of semiconductor material and in integral relation with said N-type substrate layer. c. said forming said third region includes epitaxially growing an N-type layer of semiconductor material upon said P-type layer of semiconductor material, d. said forming said second channel portion of said opposite conductivity type semiconductor material includes diffusing a P+ channel portion through said N-type third layer of semiconductor material and in integral relation with said P-type second layer of semiconductor material, and e. reverse biasing the P-type regions of semiconductor material with respect to the adjacent N-type regions of semiconductor material whereby electrical potentials may be distributed within said P-type and N-type regions of semiconductor material and to the surface of a monolithic integrated structure formed by said layers.
References Cited (Backward Citations)
US3395320A
Cited
US3387193A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-19 | 1976-06-19 | 1976-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-19 | 1980-06-19 | 1980-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-19 | 1984-06-19 | 1984-12-19 | $7700.00 | Window Closed / Lapsed |