Multiple-phase logic circuits

Claim 2

In combination: a logic circuit responsive to signals indicative of a plurality of variables present during a first time interval for producing a first output H indicative of a logic function of these variables during at least a portion of this time interval; first control circuit means for sensing the value of this output H during one portion of said first time interval for producing an output F indicative of said logic function during a second time interval; and second control circuit means for sensing the value of output H during another portion of said first time interval, for producing an output indicative of the same logic function as F during a third time interval different than said second time interval.

Claim 3

The combination set forth in claim 1 further including means for producing successive clock pulses phi 1, phi 2, phi 3, phi 4, and wherein said signals indicative of variables are present during the interval of clock pulses phi 2 and phi 3, wherein said first control circuit means includes means for sensing the value of said output H of said logic circuit during the interval of clock pulse phi 2 and includes means for storing said output F during the interval of clock pulses phi 3 and phi 4, and wherein said second control means includes means for sensing the value of H during the interval of clock pulse phi 3 and means for storing said output it produces for a third time interval of duration equal to that of clock pulses phi 4 and phi 1.

Claim 4

In combination: a logic circuit comprising a plurality of field-effect transistors the conduction paths of which are interconnected between first and second circuit nodes; means for applying input signals indicative of binary variables to the gate electrodes of said transistors during a first time interval for causing a low impedance via the conduction paths of one or more of said transistors to exist between said two nodes for given combinations of said variables and for causing a high impedance to exist between said two nodes for the remaining comBinations of said variables; a third circuit node; means for charging said third circuit node to a voltage level indicative of a bit of given binary value during a first clock pulse interval prior to the time said information signals are present; a switch connected between said third and said second nodes; means responsive to a second clock pulse which occurs during the time said input signals are present for closing said switch; means for placing said first circuit node at a point of reference potential concurrently with the closing of said switch; a fourth circuit node; means for charging said fourth circuit node to a voltage level indicative of said bit of given binary value during said second clock pulse interval; a fifth circuit node; a switch in a path connected at one end to said fifth circuit node and having also a second end, said switch coupled to said third circuit node and controlled by the voltage present at said third circuit node; means responsive to a third clock pulse after said second clock pulse for connecting said fourth circuit node to the second end of said path; and means for placing said fifth circuit node at a point of reference potential during said third clock pulse.

Claim 5

In combination: a logic circuit comprising a plurality of field-effect transistors the conduction paths of which are interconnected between first and second circuit nodes; means for applying input signals indicative of binary variables to the gate electrodes of said transistors during a first time interval for causing a low impedance via the conduction paths of one or more of said transistors to exist between said two nodes for given combinations of said variables and for causing a high impedance to exist between said two nodes for the remaining comBinations of said variables; a third circuit node; means for charging said third circuit node to a voltage level indicative of a bit of given binary value during a first clock pulse interval prior to the time said information signals are present; a switch connected between said third and said second nodes; means responsive to a second clock pulse which occurs during the time said input signals are present for closing said switch; means for placing said first circuit node at a point of reference potential concurrently with the closing of said switch; a fourth circuit node; means for charging said fourth circuit node to a voltage level indicative of said bit of given binary value during said second clock pulse interval; a fifth circuit node; a switch in a path connected at one end to said fifth circuit node and having also a second end, said switch coupled to said third circuit node and controlled by the voltage present at said third circuit node; means responsive to a third clock pulse after said second clock pulse for connecting said fourth circuit node to the second end of said path; and means for placing said fifth circuit node at a point of reference potential during said third clock pulse.

Claim 6

In combination: a logic circuit comprising a network of switches connected between first and second circuit nodes; means responsive to input signals indicative of binary variables for controlling said switches to provide at least one low impedance path, via at least one closed switch, between said two nodes for given combinations of values of the said binary variables and to provide a high impedance between said two nodes for the remaining combinations of values of said binary variables; a third circuit node; means for charging said third circuit node to a voltage level indicative of a bit of given binary value during a first clock pulse interval prior to the time said information signals are present; a first control switch connected between said third and said second nodes; means responsive to a second clock pulse which occurs during the time said input signals are present for closing said first control switch; means for placing said first circuit node at a point of reference potential concurrently with the closing of said first control switch; a fourth circuit node; means for charging said fourth circuit node to a voltage level indicative of said bit of given binary value during said second clock pulse interval; a fifth circuit node; a switch in a path connected at one end to said fifth circuit node and having also a second end, said switch coupled to said third circuit node and controlled by the voltage present at said third circuit node; means responsive to a third clock pulse after said second clock pulse for connecting said fourth circuit node to the second end of said path; and means for placing said fifth circuit node at a point of reference potential during said third clock pulse.

Claim 7

In combination: a logic circuit comprising a network of switches connected between first and second circuit nodes; means responsive to input signals indicative of binary variables for controlling said switches to provide at least one low impedance path, via at least one closed switch, between said two nodes for given combinations of values of the said binary variables and to provide a high impedance between said two nodes for the remaining combinations of values of said binary variables; a third circuit node; means for charging said third circuit node to a voltage level indicative of a bit of given binary value during a first clock pulse interval prior to the time said information signals are present; a first control switch connected between said third and said second nodes; means responsive to a second clock pulse which occurs during the time said input signals are present for closing said first control switch; means for placing said first circuit node at a point of reference potential concurrently with the closing of said first control switch; a fourth circuit node; means for charging said fourth circuit node to a voltage level indicative of said bit of given binary value during said second clock pulse interval; a fifth circuit node; a switch in a path connected at one end to said fifth circuit node and having also a second end, said switch coupled to said third circuit node and controlled by the voltage present at said third circuit node; means responsive to a third clock pulse after said second clock pulse for connecting said fourth circuit node to the second end of said path; and means for placing said fifth circuit node at a point of reference potential during said third clock pulse.

Claim 8

In the combination as set forth in claim 4 all of said switches comprising field-effect transistors.

Claim 9

In a logic circuit as set forth in claim 5 all of said field-effect transistors being of the same conductivity type.

Claim 10

In the combination as set forth in claim 4, each means for charging comprising a field-effect transistor connected gate electrode-to-drain electrode and connected at its source electrode to the circuit node being charged.

Claim 11

In combination: a logic circuit responsive to signals indicative of a plurality of variables present during a first time interval for producing a first output H indicative of a logic function of these variables during at least a portion of this time interval; first control circuit means for sensing the value of this output H during one portion of said first time interval for producing an output F indicative of said logic function during a second time interval; and second control circuit means for sensIng the value of F during at least a portion of said second time interval, for producing an output E indicative of the complement of F during a third time interval different than said second time interval.

Claim 12

In combination: a logic circuit responsive to signals indicative of a plurality of variables present during a first time interval for producing a first output H indicative of a logic function of these variables during at least a portion of this time interval; first control circuit means for sensing the value of this output H during one portion of said first time interval for producing an output F indicative of said logic function during a second time interval; and second control circuit means for sensIng the value of F during at least a portion of said second time interval, for producing an output E indicative of the complement of F during a third time interval different than said second time interval.