US3710374A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual-slope and analog-to-digital converter wherein two analog input signals are selectively integrated with respect to time
Assignee: WESTER INSTR Inc
•
Filing: 1970-08-17
•
Granted: 1973-01-09
•
Expires: 1990-08-17
Abstract
Abstract An electrical integrating circuit arrangement is disclosed which is especially suitable for use in combination with timing means in dual-slope analog-to-digital converters because it operates with time controlled closure of a single, low-impedance switching device of the single-pole, single-throw type to effect selective time integrations of two D.C. input signals; an analog signal and an oppositely directed reference current. The integrating arrangement comprises an operational amplifier having inverting and non-inverting inputs and feedback to the inverting input through a capacitor. The analog signal source may be permanently connected to the non-inverting input whereas the second input signal is similarly connected to the inverting input through a resistance. The switching device is closed to connect the second input signal end of the resistance to a source of potential. Timed closure of the switching device by the timing means causes the integrating arrangement to generate two successive voltage ramps having slopes which are respective functions of the two signals exclusive of one another. The instant combination may be utilized to advantage in the digitalization of bipolar analog signals.
Inventors
- 👤 A Kelly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:07
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
361 words
An analog-to-digital conversion system for producing a digital representation of the magnitude of an analog input signal of unknown magnitude comprising: a differential amplifier having inverting input, non-inverting input and output terminals, means for applying an analog signal to the non-inverting input terminal continuously during an analog-to-digital conversion cycle comprising first and second successive time intervals, reactive feedback means coupling said output terminal to said inverting terminal whereby the voltage at said inverting terminal is at all times linearly related and substantially equal to, the analog signal, a source of electrical current of constant magnitude, electrical resistance means connecting the current source to said inverting input terminal and with said reactive means comprising integrating means, switch means for selectively connecting the current source end of said resistance means to a source of fixed potential having a magnitude referenced to the full scale magnitude of the analog signal, whereby one current proportional to the potential at said non-inverting input terminal flows through said resistance means in a first direction during the first time interval when said switch means connects said potential source to said current source, said first time interval including a variable time interval and a fixed time interval, the variable time interval being a function of the analog signal magnitude and preceding the fixed time interval, said current source having a polarity such that current therefrom flows through said resistance means in a second direction opposite said first direction during the second time interval when said switch means disconnects said potential source from said current source, means including digital timing means for fixing the time duration of said fixed time interval coupled to said switch means for time controlling the state thereof such that said one current flows through said resistance means in said first direction for said fixed first time interval followed by current flow from said current source through said resistance means in said second direction, and means coupled to said output terminal of said differential amplifier and to said timing means for causing said timing means to also digitally time the current flow in said second direction to provide a digital representation of the analog signal magnitude.
Claim 2
Dependent Claim
361 words
An analog-to-digital conversion system for producing a digital representation of the magnitude of an analog input signal of unknown magnitude comprising: a differential amplifier having inverting input, non-inverting input and output terminals, means for applying an analog signal to the non-inverting input terminal continuously during an analog-to-digital conversion cycle comprising first and second successive time intervals, reactive feedback means coupling said output terminal to said inverting terminal whereby the voltage at said inverting terminal is at all times linearly related and substantially equal to, the analog signal, a source of electrical current of constant magnitude, electrical resistance means connecting the current source to said inverting input terminal and with said reactive means comprising integrating means, switch means for selectively connecting the current source end of said resistance means to a source of fixed potential having a magnitude referenced to the full scale magnitude of the analog signal, whereby one current proportional to the potential at said non-inverting input terminal flows through said resistance means in a first direction during the first time interval when said switch means connects said potential source to said current source, said first time interval including a variable time interval and a fixed time interval, the variable time interval being a function of the analog signal magnitude and preceding the fixed time interval, said current source having a polarity such that current therefrom flows through said resistance means in a second direction opposite said first direction during the second time interval when said switch means disconnects said potential source from said current source, means including digital timing means for fixing the time duration of said fixed time interval coupled to said switch means for time controlling the state thereof such that said one current flows through said resistance means in said first direction for said fixed first time interval followed by current flow from said current source through said resistance means in said second direction, and means coupled to said output terminal of said differential amplifier and to said timing means for causing said timing means to also digitally time the current flow in said second direction to provide a digital representation of the analog signal magnitude.
Claim 3
Dependent Claim
14 words
The system according to claim 1 wherein said source of fixed potential is ground.
Claim 4
Dependent Claim
28 words
The system according to claim 1 wherein the absolute magnitude of said source of fixed potential is greater than the full scale voltage magnitude of the analog signal.
Claim 5
Dependent Claim
25 words
The system according to claim 3 wherein said source of fixed potential has a polarity determined by the polarity of the full scale analog signal.
Claim 6
Dependent Claim
26 words
The system according to claim 4 wherein the polarity of said source of fixed potential is the same as that of the full scale analog voltage.
Claim 7
Dependent Claim
24 words
The system according to claim 4 wherein the polarity of the source of fixed potential is opposite that of the full scale analog voltage.
Claim 8
Dependent Claim
72 words
The system according to claim 1 wherein said switch means has open and closed states and which further comprises, a junction common to one end of said switch meaNs, said source of electrical current and said electrical resistance means; the value of said electrical resistance means being substantially greater than the resistance of the electrical circuit created between said junction and said source of fixed potential upon closure of said switch means.
Claim 9
Dependent Claim
44 words
The system according to claim 7 wherein the analog signal has a predetermined full scale voltage magnitude VA(FS), and wherein the relation between said voltage and the voltage VB produced by said source of fixed potential is, VB NVA(FS); where N is a constant.
Claim 10
Dependent Claim
59 words
The system according to claim 8 wherein the fixed potential source has a low impedance and N is substantially equal to zero and wherein said source of electrical current and said switch means has one terminal thereof commonly coupled to said junction, whereby closure of said switch means shunts the source of electrical current to said fixed potential source.
Claim 11
Dependent Claim
120 words
The system according to claim 1 wherein comprises, means for clamping the potential at said differential amplifier output at essentially one level prior to closure of said switch means and to said first time interval, and voltage comparison means coupled to said differential amplifier output terminal and to said differential amplifier inverting input terminal and producing an output signal in response to the potential at said differential amplifier output at least equalling that at said inverting input terminal upon closure of said switch means, said comparison means thereby establishing a threshold level different from that of said one level and about which threshold level said differential amplifier output potential departs and returns in said fixed and second time intervals, respectively.
Claim 12
Dependent Claim
36 words
The system according to claim 10 wherein said timing means comprises, pulse counting means coupled to said voltage comparison means and responsive to the output signal thereof for initiating the timing of said first time interval.
Claim 13
Dependent Claim
51 words
The system according to claim 11 wherein said pulse counting means comprises a plurality of counting stages, and means coupling a selected one of said counting stages to said switch means and means responsive to a counting transition in the one stage for driving said switch means to the open state.
Claim 14
Dependent Claim
58 words
The converter according to claim 12 wherein said means responsive to said counting transition comprises, a bistable device and which further comprises, means for resetting said pulse counter to a predetermined starting count and said bistable device at least prior to said first time interval, said bistable device when reset driving said switching device to the closed state.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-09 | 1976-07-10 | 1977-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-09 | 1980-07-10 | 1981-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-09 | 1984-07-10 | 1985-01-09 | $7700.00 | Window Closed / Lapsed |