Data regeneration scheme for stored charge storage cell

Claim 2

In a matrix of stored charge memory cells each addressed by the selection of a plurality of lines out of a grid of addressing lines for the matrix, a data regeneration scheme for periodically restoring the data stored in the memory cell without reading data out of the matrix, comprising: read means for reading the data stored in anY given cell out onto one of the plurality of lines for addressing the cell; storage means connected directly to said one of the plurality of lines for temporarily storing the data so read out on said one of said plurality of lines so that it can be later read back into the given storage cell; and write means for writing the data stored in the storage means back into the given storage cell.

Claim 3

The memory matrix of claim 1 wherein the storage means includes: the line capacitance of said one of said plurality of lines; and restoration means for restoring the charge on said line capacitance after a regeneration cycle consisting of reading the data stored in said given cell onto the line capacitance and writing the data so stored on the line capacitance back into said given cell.

Claim 4

In a word oriented matrix of three semiconductor device memory cells with the first device storing data in the form of charge on one of its interelectrode capacitances and the other two devices coupling said first device to word and bit line means for addressing the particular cell, a data regeneration scheme for periodically restoring the data stored in the memory cell comprising: read means coupled to the word line means for rendering one of said other two devices in a particular cell conductive to thereby read the data stored in any particular cell onto the bit line means for said particular cell; storage means coupled to said bit line means for temporarily storing the data read out from the particular cell onto the bit line means, and write means coupled to the word line means to render the second of the other two devices to write the data stored in the storage means back into said particular cell.

Claim 5

In a word oriented matrix of three semiconductor device memory cells with the first device storing data in the form of charge on one of its interelectrode capacitances and the other two devices coupling said first device to word and bit line means for addressing the particular cell, a data regeneration scheme for periodically restoring the data stored in the memory cell comprising: read means coupled to the word line means for rendering one of said other two devices in a particular cell conductive to thereby read the data stored in any particular cell onto the bit line means for said particular cell; storage means coupled to said bit line means for temporarily storing the data read out from the particular cell onto the bit line means, and write means coupled to the word line means to render the second of the other two devices to write the data stored in the storage means back into said particular cell.

Claim 6

The memory cell of claim 3 wherein said storage means includes: the line capacitance of said bit line means; and restoration means for restoring the charge on said line capacitance after a regeneration cycle consisting of reading the data stored in the particular cell and writing the data as stored on the line capacitance back into the particular cell.

Claim 7

The memory matrix of claim 4 including means for accessing said read means, said write means and said restoration means to perform two regeneration cycles and to restore the charge on said line capacitance between said regeneration cycles.

Claim 8

The memory matrix of claim 3 wherein said three device cells includes: one device storing the data in its interelectrode capacitance; a second device for charging and discharging the charge on the interelectrode capacitance to write data into the three device cell; and a third device for determining the charge stored on the interelectrode capacitance to read the data stored in the storage cell.

Claim 9

The memory matrix of claim 6 wherein said devices are field effect transistors.