US3716843A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modular signal processor
Assignee: Lockheed Martin Corp
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Filing: 1971-12-08
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Granted: 1973-02-13
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Expires: 1991-12-08
Abstract
Abstract A modular signal processor which is assembled from a set of modules which have common input and output timing specifications such that any one module can be interconnected with any other module to perform a desired signal processing operation under the control of a timing generator. The timing generator is arranged to produce a clock signal of relatively high frequency and sequences of timing signals at a relatively lower frequency. Data is loaded into a module in response to a first one of the timing signal. The module then performs its operation or function upon the data to provide a result data. The result data is then read from the module in response to a subsequently occurring timing signal which is also employed to load the result data into another module. Specifically disclosed herein is a frequency synthesizer processor which employs the following modules: binary coded decimal to binary converter, phase accumulator, look up table and a digital to analog converter and filter.
Inventors
- 👤 J Schmitt
- 👤 D Starkey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; H; H03; H03B; H03B21/00; H03B21/01; H03B21/02; H03B21/025
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
258 words
The combination comprising: a timing generator for producing a clock signal at a relatively high frequency and for producing at a lower frequency sequences of timing signals; first and second modules, each including an input register, an output register, a function generator and a timing section; the timing section of the first module including means responsive to a first of said timing signals and to said clock signal to load the first module input register with input data, second means responsive to said clock signal to enable the first module function generator to perform its function on said input data to provide a first result data and to load said first result data into said first module output register, and third means responsive to a second subsequent one of said timing signals and to said clock signal to read said first data result from said first module output register; and the timing section of said second module including first means responsive to said second timing signal and to said clock signal to load said first data into the second module input register, second means responsive to said clock signal to enable the second module function generator to perform its function on said first result data to produce second result data and to load said second result data into said second module output register, and third means responsive to said clock signal and to a third one of said timing signals subsequent to said second timing signal to read said second result data from said second module output register.
Claim 2
Dependent Claim
258 words
The combination comprising: a timing generator for producing a clock signal at a relatively high frequency and for producing at a lower frequency sequences of timing signals; first and second modules, each including an input register, an output register, a function generator and a timing section; the timing section of the first module including means responsive to a first of said timing signals and to said clock signal to load the first module input register with input data, second means responsive to said clock signal to enable the first module function generator to perform its function on said input data to provide a first result data and to load said first result data into said first module output register, and third means responsive to a second subsequent one of said timing signals and to said clock signal to read said first data result from said first module output register; and the timing section of said second module including first means responsive to said second timing signal and to said clock signal to load said first data into the second module input register, second means responsive to said clock signal to enable the second module function generator to perform its function on said first result data to produce second result data and to load said second result data into said second module output register, and third means responsive to said clock signal and to a third one of said timing signals subsequent to said second timing signal to read said second result data from said second module output register.
Claim 3
Dependent Claim
258 words
The combination comprising: a timing generator for producing a clock signal at a relatively high frequency and for producing at a lower frequency sequences of timing signals; first and second modules, each including an input register, an output register, a function generator and a timing section; the timing section of the first module including means responsive to a first of said timing signals and to said clock signal to load the first module input register with input data, second means responsive to said clock signal to enable the first module function generator to perform its function on said input data to provide a first result data and to load said first result data into said first module output register, and third means responsive to a second subsequent one of said timing signals and to said clock signal to read said first data result from said first module output register; and the timing section of said second module including first means responsive to said second timing signal and to said clock signal to load said first data into the second module input register, second means responsive to said clock signal to enable the second module function generator to perform its function on said first result data to produce second result data and to load said second result data into said second module output register, and third means responsive to said clock signal and to a third one of said timing signals subsequent to said second timing signal to read said second result data from said second module output register.
Claim 4
Dependent Claim
258 words
The combination comprising: a timing generator for producing a clock signal at a relatively high frequency and for producing at a lower frequency sequences of timing signals; first and second modules, each including an input register, an output register, a function generator and a timing section; the timing section of the first module including means responsive to a first of said timing signals and to said clock signal to load the first module input register with input data, second means responsive to said clock signal to enable the first module function generator to perform its function on said input data to provide a first result data and to load said first result data into said first module output register, and third means responsive to a second subsequent one of said timing signals and to said clock signal to read said first data result from said first module output register; and the timing section of said second module including first means responsive to said second timing signal and to said clock signal to load said first data into the second module input register, second means responsive to said clock signal to enable the second module function generator to perform its function on said first result data to produce second result data and to load said second result data into said second module output register, and third means responsive to said clock signal and to a third one of said timing signals subsequent to said second timing signal to read said second result data from said second module output register.
Claim 5
Dependent Claim
44 words
The invention set forth in claim 1 wherein the timing section first and third means of each said module respond to their corresponding timing signals and to said clock signal to load or read their corresponding registers serial by bit and parallel by byte.
Claim 6
Dependent Claim
82 words
The invention set forth in claim 2 wherein each timing signal has a duration of n clock signal cycles, where n is the number of bitS in a byte; and wherein the second timing means of one of said modules also responds to the termination of the timing signal which caused its corresponding input register to be loaded, to establish a group of 2 n clock cycles which group is employed to load the corresponding data result in the corresponding output register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |