Method of making an igfet defice with reduced gate-to- drain overlap capacitance

Abstract

Abstract The disclosure teaches a method for producing an IGFET device characterized by an extremely narrow gate area with no overlapping of the source and drain regions. A controlled etch is used to form a pattern in a first layer over the substrate to precisely define the gate width. The substrate is subsequently oxidized so that the material covering the gate area can be preferentially etched away, thereby creating a window precisely defining the gate electrode. The need for precisely registering masks is avoided. A superior IGFET with greater speed of response and other concomitant advantages results.

Inventors

• 👤 D Zoroglu

Bibliographic Details