System for determining direction of arrival of signals

Claim 3

A system as defined in claim 1, and wherein said first and second means each comprises a pulse time comparison circuit comprising: OR gate means for providing as an output pulses each of which begins with the leading edge of a leading pulse input derived from one of said probes of a pair and ends with the trailing edge of a lagging pulse input derived from the other of said probes of that pair; first coincidence gate means for providing as an output pulses each having a width equaling the period of coincidence of said leading and lagging pulse inputs; flip-flop means, responsive to the outputs of said OR gate means and said first coincidence gate means, for producing a first output condition which begins with the leading edge of said lagging pulse and ends with the trailing edge of said lagging pulse and a second output condition at all other times; second coincidence gate means, responsive to said pulses derived from said one of said probes and to said output conditions of said flip-flop means, for providing output pulses having widths equaling the times during which said pulses derived from said one of said probes lead the pulses derived from said other of said probes; third coincidence gate means, responsive to said pulses derived from said other of said probes and to said output conditions of said flip-flop means, for providing output pulses having widths equaling the times during which said pulses derived from said other of said probes lead the pulses derived from said one of said probes; and NOR gate means for providing on a common output line the outputs of said second and third coincidence gate means as one of said first and second series of pulses.

Claim 4

A system as defined in claim 2, and wherein said means for averaging portions of said first and second series of pulses comprises: pulse selector circuit means, responsive to said first and second series of pulses as inputs, for rejecting a first predetermined number of pulses in one of said series, then selecting a second predetermined number of output pulses corresponding in width to pulses in said one of said series, and then selecting a third predetermined number of pulses but corresponding in width to pulses of the other of said series of pulses, whereby the output of said pulse selector circuit means consists of equal numbers of pulses having widths corresponding to said first and second series.

Claim 5

A system as defined in claim 3, and further comprising: clock means for providing clock signals of predetermined frequency; gate means, responsive to said output pulses of said selector circuit means, for passing numbers of said clock signals proportional in number to widths of said output pulses of said selector circuit means; and counter means, responsive to said signals passed by said gate means, for providing a count proportional to the average width of said output pulses of said selector circuit means and hence to cos theta .

Claim 6

A system as defined in claim 4, and comprising: second flip-flop means, responsive to the output of said second coincidence gate means, for providing first and second output conditions indicative of which of said probes of one of said pairs received said waves prior to the other, whereby ambiguity of direction of arrival of said waves is avoided.

Claim 7

A system as defined in claim 5, and wherein said pulse selector circuit comprises: fourth coincidence gate means for providing, when enabled, output pulses in response to said first series of pulses; fifth coincidence gate means for providing, when enabled, output pulses in response to said second series of pulses; third and fourth flip-flop means for providing signals for alternatively enabling said fourth and fifth coincidence gate means; a second NOR gate means for providing on a common line output corresponding to the outputs of said fourth and fifth coincidence gate means; second counter means, responsive to the outpUt of said second NOR gate means, for providing signals corresponding to said first predetermined number, said second predetermined number, and said third predetermined number; sixth and seventh coincidence gate means, connected in series with the output of said second NOR gate means, for providing output pulses from said second NOR gate means when both said sixth and seventh coincidence gates are enabled, but preventing such output when either is disabled; fifth flip-flop means, responsive to said counter signal corresponding to said first predetermined number, for providing a condition which enables said seventh coincidence gate means; eighth coincidence gate means, responsive to said signals corresponding to said second predetermined number, for causing said third flip-flop means to reverse its condition so as to disable said fourth coincidence gate means and to permit said fourth flip-flop means to reverse its condition at the next trailing edge of a pulse of said second series so as to enable said fifth coincidence gate means; ninth coincidence gate means for providing an output in response to said signals corresponding to said third predetermined number; and sixth flip-flop means, responsive to said output of said ninth coincidence gate means, for disabling said sixth coincidence gate means, whereby the output of said pulse selector circuit is interrupted.

Claim 8

A system as defined in claim 6, and wherein: said second and third predetermined numbers are equal.