← Back to Patent Explorer
US3731216A Expired / Lapsed US ⏱️ 0.0 years remaining

Automatic gain control circuit

Assignee: Sony Corp
•
Filing: 1971-06-23
•
Granted: 1973-05-01
•
Expires: 1991-06-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An automatic gain control amplifier has at least two amplifier stages forming a transmission line for an input signal with one of the stages constituted by a transistor and the other stage constituted by a field effect transistor. A reverse automatic gain control signal for the field effect transistor is derived from the output of the transmission line and a forward automatic gain control signal responsive to a current flowing through the field effect transistor is applied to the transistor, and improper bias of the transistor is suppressed so as to maintain the latter at its proper quiescent DC bias.

Inventors

  • 👤 H Nakamura
  • 👤 K Morii

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 03:21
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 238 words
An automatic gain control amplifier comprising at least two amplifier stages connected to each other to constitute a transmission line for an input signal, one of said amplifier stages being constituted by a transistor and the other of said amplifier stages being constituted by a field effect transistor, means for supplying to said field effect transistor an automatic gain control signal which varies in accordance with the level of said input signal and is derived from the output of said transmission line and which decreases a current through said field effect transistor for decreasing the gain of the latter in response to an increase in the level of said input signal thereby to exert a reverse AGC action on said field effect transistor, means responsive to said current through the field effect transistor for varying a bias voltage of said transistor of said one amplifier stage in the direction for increasing a current flowing through said transistor, and thereby reducing the gain of the latter, in accordance with reductions of said current through the field effect transistor for exerting a forward AGC action on said transistor of said one amplifier stage, and means for automatically suppressing improper bias of the transistor of said one amplifier stage and including means establishing a reference potential interconnected with said means responsive to the current through the field effect transistor for maintaining said transistor at least at its proper quiescent DC bias.
Claim 2
Dependent Claim 238 words
An automatic gain control amplifier comprising at least two amplifier stages connected to each other to constitute a transmission line for an input signal, one of said amplifier stages being constituted by a transistor and the other of said amplifier stages being constituted by a field effect transistor, means for supplying to said field effect transistor an automatic gain control signal which varies in accordance with the level of said input signal and is derived from the output of said transmission line and which decreases a current through said field effect transistor for decreasing the gain of the latter in response to an increase in the level of said input signal thereby to exert a reverse AGC action on said field effect transistor, means responsive to said current through the field effect transistor for varying a bias voltage of said transistor of said one amplifier stage in the direction for increasing a current flowing through said transistor, and thereby reducing the gain of the latter, in accordance with reductions of said current through the field effect transistor for exerting a forward AGC action on said transistor of said one amplifier stage, and means for automatically suppressing improper bias of the transistor of said one amplifier stage and including means establishing a reference potential interconnected with said means responsive to the current through the field effect transistor for maintaining said transistor at least at its proper quiescent DC bias.
Claim 3
Dependent Claim 43 words
An automatic gain control amplifier according to claim 1, wherein said means for suppressing improper bias includes a resistive voltage divider, and a Zener diode connected between the divider output and a bias circuit input of said transistor of said one amplifier stage.
Claim 4
Dependent Claim 46 words
An automatic gain control circuit according to claim 2, wherein said transistor of said one amplifier stage has a bias circuit comprising a first resistor connected between the base of said transistor and ground and a second resistor connected between said base and said Zener diode.
Claim 5
Dependent Claim 50 words
An automatic gain control amplifier according to claim 2, wherein a single power supply terminal is connected in series with the drain-source terminals of the field effect transistor and a current limiting resistor, and said Zener diode and one resistor of said resistive voltage divider shunt said current limiting resistor.
Claim 6
Dependent Claim 31 words
An automatic gain control amplifier according to claim 2, wherein said means for suppressing improper bias includes means constituting a capacitive connection to ground at the output of the Zener diode.
Claim 7
Dependent Claim 24 words
An automatic gain control amplifier according to claim 1, in which said one amplifier stage precedes said other amplifier stage in said transmission line.
Claim 8
Dependent Claim 32 words
An automatic gain control amplifier according to claim 6, in which said transistor has its emitter capacitively connected to ground and said field effect transistor has its gate capacitively connected to ground.
Claim 9
Dependent Claim 24 words
An automatic gain control amplifier according to claim 1, in which said one amplifier stage follows said other amplifier stage in said transmission line.
Claim 10
Dependent Claim 32 words
An automatic gain control amplifier according to claim 8, in which said field effect transistor has its source capacitively connected to ground and said transistor has its base capacitively connected to ground.
Claim 11
Dependent Claim 97 words
An automatic gain control amplifier according to claim 1, in which said automatic gain control signal decreases negatively with increasing levels of said input signal and is applied as a negative bias potential to the gate of said field effect transistor so that the drain current of the latter decreases to decrease said gain of the field effect transistor in accordance with an increasing level of said input signal, and said decreasing drain current of the field effect transistor causes an increase in the base potential of said transistor for increasing said current flowing through the transistor.

References Cited (Backward Citations)

US3440543A Cited
US3388338A Cited
US3404347A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-04-30 1976-10-30 1977-05-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-04-30 1980-10-30 1981-05-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-04-30 1984-10-30 1985-05-01 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag