Multiple phase clock generator circuit with control circuit

Claim 2

A multiple phase clock signal generator comprising, an RC oscillator circuit generating multiple and phase related square save signals, a control circuit receiving said square wave signals including means for phase ordering said signals to prevent phase overlapping between the signals, a multi-bit shift register in which outputs from certain bit positions of the shift register are inverted and fed back as inputs to other bit positions of the shift register, said shift register being gated by the signals generated by said control circuit, and output logic gates generating multiphase clock signals in response to outputs from said shift register and in response to certain multiphase clock signals fed back from the outputs of said logic gates for providing a synchronized relationship between the multiphase clock signals being generated.

Claim 3

The multiple phase clock signal generator recited in claim 1 wherein said control circuit comprises logic gates having square wave output signals which are fed back to the inputs of different ones of the logic gates for ordering the phase relative to the square wave signals generated by the oscillator circuit.

Claim 4

A multiple phase clock signal generator recited in claim 2 wherein said control circuit further comprises two NOR gates receiving two square wave signals as inputs from said RC oscillator circuit, said NOR gates inverting the phase of the input square waves, the outputs from each NOR gate being fed back as an input to the other NOR gate for preventing phase overlapping between the phases of the square wave signals provided at the outputs of said NOR gates.

Claim 5

The multiphase clock signal generator recited in claim 1 wherein said multi-bit shift register has a plurality of bit positions determined as a function of the number of phases of said multiphase clock signals.

Claim 6

The multiphase clock signal generator recited in claim 2 wherein the RC time constant of said RC oscillator is selected for generating said square wave signals with a cycle equivalent to one phase of said multiphase clock signals.

Claim 7

The multiphase clock signal generator recited in claim 3 wherein said RC oscillator circuit, said multi-bit shift register, and said output logic gates, are implemented by field effect transistors.

Claim 8

The multiphase clock signal generator recited in claim 1 wherein said RC oscillator circuit includes first and second inverter circuits responsive to the charge and discharge voltage levels of the RC circuit for providing a first square wave output signal from said RC oscillator circuit, and a third inverter responsive to said first square wave output signal for providing a second square wave output signal having an opposite phase from said first signal, said control circuit including two NOR gates for phase inverting said first and second square wave signals, the second phase inverted square wave signal being applied to said multi-bit shift register for gating information into said multi-bit shift register, and said first phase inverted square wave signal being applied to said multi-bit shift register for gating information out of said shift register.

Claim 9

The multiphase clock signal generator recited in claim 7 wherein said multi-bit shift register comprises two bit positions, and said output logic gates comprise four logic gates for generating four multiphase clock signals.

Claim 10

The multiphase clock signal generator recited in claim 8 wherein said multi-bit shift register includes inverters for inverting the output from both bit positions of two bit shift register, and said output logic gates comprise four NOR gates responsive to the output signals from both bit positions of said shift register and to the inverted outputs from said bit positions, and responsive to signals fed back from the outputs of said NOR gates for generating four phase related clock signals comprising said multiphase clock signals, said NOR gates including output stages comprising field effect transistors having a size relative to each other for preventing both field effect transistors from being on simultaneously.

Claim 11

The multiphase clock signal generator recited in claim 9 wherein two of said multiphase clock signals have a clock signal width which is twice as large as the clock signal width of the remaining two clock signals.

Claim 12

A multiple phase clock signal generating circuit comprising, oscillator circuit means for supplying regularly recurring signals, control circuit means connected to said oscillator circuit for receiving signals therefrom and producing output signals which are a function of the inverted signals from said oscillator circuit, shift register means for receiving signals from said control circuit means wherein said signals from said control circuit means control the operation of said shift register means, and output means including a plurality of gate means, each of said gate means having a plurality of input terminals and an output terminal, at least one of said input terminals of each of said gate means connected to said shift register means to receive signals therefrom, the output terminals of some of said gate means connected to the other input terminals of said gate means whereby said output means produces output signals representative of the signals received from said shift register means.

Claim 13

A multiple phase clock signal generating circuit comprising, oscillator circuit means for supplying regularly recurring signals, control circuit means connected to said oscillator circuit for receiving signals therefrom and producing output signals which are a function of the inverted signals from said oscillator circuit, shift register means for receiving signals from said control circuit means wherein said signals from said control circuit means control the operation of said shift register means, and output means including a plurality of gate means, each of said gate means having a plurality of input terminals and an output terminal, at least one of said input terminals of each of said gate means connected to said shift register means to receive signals therefrom, the output terminals of some of said gate means connected to the other input terminals of said gate means whereby said output means produces output signals representative of the signals received from said shift register means.