Abstract The invention relates to digital circuitry for automatically upon receipt of a calibrate signal locking on to received analog data and decommutating said data for further processing. The circuit locks on to the beginning of each frame and maintains this lock on while a counter counts the segments of the frame and resets the circuitry for the receipt of a new frame upon the end of the previous frame. The digital data is comprised of 32 segments the first two of which are approximately all zeros and approximately all ones. The remainder of which are at varying digital levels between all zeros and all ones. The calibrate circuit looks for the calibrate signal, all zeros and then for all ones before allowing the data to go on for further processing in the digital to analog converter.
A calibrate lock on circuit comprising: analog to digital converter means for converting varying analog level segments, which comprise a frame of information, into separate digital word segments, said converter means including integrator means for integrating said digital word segments; said frame being received at random times; detecting means for detecting the beginning of said frames; said detecting means being coupled to said converter means; counting means connected to said detecting means for counting said digital word segments; said integrator being responsive to the segment count of said counting means; said counting means being connected to output means and including means for supplying said output means with the location of each segment in each frame; said output means being connected to said converter means to receive said digital segments; said output means including means for converting said digital segments to analog segments.
Claim 2
Dependent Claim
142 words
A calibrate lock on circuit comprising: analog to digital converter means for converting varying analog level segments, which comprise a frame of information, into separate digital word segments, said converter means including integrator means for integrating said digital word segments; said frame being received at random times; detecting means for detecting the beginning of said frames; said detecting means being coupled to said converter means; counting means connected to said detecting means for counting said digital word segments; said integrator being responsive to the segment count of said counting means; said counting means being connected to output means and including means for supplying said output means with the location of each segment in each frame; said output means being connected to said converter means to receive said digital segments; said output means including means for converting said digital segments to analog segments.
Claim 3
Dependent Claim
31 words
The circuit of claim 1 wherein said detecting means includes at least two comparators each of said comparators being responsive to particular digital words thereby detecting the beginning of said frames.