US3745470A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse transmitter circuit for measuring instruments
Assignee: Caterpillar Inc
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Filing: 1971-05-28
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Granted: 1973-07-10
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Expires: 1991-05-28
Abstract
Abstract A compact, economically manufactured circuit for generating and transmitting pulses in response to predetermined increments of rotation of an element of a fluid flow meter has a photosensitive component detecting rotation of the meter element. Additional components, including an operational amplifier and logic gates, amplify and shape the signals from the photosensitive component and double the signal frequency to achieve a high pulse frequency capability, uniform pulse shape, good resolution and reliable operation in the presence of severe environmental conditions around the flow meter.
Inventors
- 👤 R Grob
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:10
CPC Classifications
G; G01; G01F; G01F1/00; G01F1/05; G01F1/10; G01F1/103; G01F15/00; G01F15/07; G01F15/075; G01F15/0755; H; H03; H03K; H03K3/00; H03K3/02; H03K3/42
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
241 words
A pulse generating and transmitting circuit for responding to a recurrent phenomenon by producing electrical output pulses at a frequency greater than that of said recurrent phenomenon comprising: transducer means for detecting said phenomenon and for producing an electrical signal in response to each recurrence thereof, an amplifier having an input coupled to said transducer means for receiving said signals therefrom and having an output at which an amplified pulse is generated in response to each of said signals, an output NAND gate means of the form having a pair of inputs and having an output at which a substantially square wave pulse is produced in response to an imbalance of electrical potential at said inputs and at which no pulse is produced when equal electrical potentials are present at each of said inputs, first and second differentiating circuits each being connected between said amplifier output and a separate one of said inputs of said output gate means to define a pair of separate pulse paths between said amplifier output and said output gate means, and means coupled to one of said pulse paths between said differentiating circuit thereof and said amplifier for inverting pulses transmitted to said output gate means through said one pulse path relative to pulses transmitted to said output gate means through said other pulse path, whereby said output gate means produces a pair of output pulses of reduced duration for each output pulse from said amplifier.
Claim 2
Dependent Claim
241 words
A pulse generating and transmitting circuit for responding to a recurrent phenomenon by producing electrical output pulses at a frequency greater than that of said recurrent phenomenon comprising: transducer means for detecting said phenomenon and for producing an electrical signal in response to each recurrence thereof, an amplifier having an input coupled to said transducer means for receiving said signals therefrom and having an output at which an amplified pulse is generated in response to each of said signals, an output NAND gate means of the form having a pair of inputs and having an output at which a substantially square wave pulse is produced in response to an imbalance of electrical potential at said inputs and at which no pulse is produced when equal electrical potentials are present at each of said inputs, first and second differentiating circuits each being connected between said amplifier output and a separate one of said inputs of said output gate means to define a pair of separate pulse paths between said amplifier output and said output gate means, and means coupled to one of said pulse paths between said differentiating circuit thereof and said amplifier for inverting pulses transmitted to said output gate means through said one pulse path relative to pulses transmitted to said output gate means through said other pulse path, whereby said output gate means produces a pair of output pulses of reduced duration for each output pulse from said amplifier.
Claim 3
Dependent Claim
89 words
A circuit as defined in claim 1 wherein said amplifier is an operational amplifier having an input signal terminal receiving said signals from said transducer means and having a reference input to which a fixed voltage is applied which fixed voltage is intermediate between the voltage extremes of said signals from said transducer means and wherein said amplifier output undergoes a transition from a first voltage level to a second voltage level in response to each change of potential at said input terminal through said fixed reference voltage level.
Claim 4
Dependent Claim
152 words
A circuit as defined in claim 1 further comprising a DC power supply and wherein each of said first said second differentiating circuits comprises a resistor connected between a single terminal of said power supply and the associated one of said inputs of said output gate means and further comprises a capacitor connected between said associated input of said output gate means and said amplifier output whereby said power supply normally provides equal potentials to said inputs of said output gate means, the potential at one of said inputs of said output gate means being momentarily changed from the potential at the other thereof by the leading edge of each output pulse from said amplifier as received through one of said two pulse paths and the potential at said other of said inputs being momentarily changed from the potential at said one thereof by the trailing edge of said amplifier output pulse.
Claim 5
Dependent Claim
94 words
A circuit as defined in claim 1 wherein said means for inverting pulses in one of said pulse paths relative to pulses in the other thereof comprises a first signal inverting means connected into one of said pulse paths and a pair of signal inverting means connected into the other of said pulse paths in series relationship whereby pulses in said other pulse paths are twice inverted whereas pulses in said first pulse path are inverted once said first signal inverting means and said pair of signal inverting means all being substantial y identical.
Claim 6
Dependent Claim
25 words
A circuit as defined in claim 4 wherein each of said signal inverting means are NAND gates substantially identical to said NAND gate output means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-09 | 1977-01-08 | 1977-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-09 | 1981-01-08 | 1981-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-09 | 1985-01-08 | 1985-07-10 | $7700.00 | Window Closed / Lapsed |