US3749836A
Expired / Lapsed
US
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Image signal converter in facsimile
Assignee: Panasonic Holdings Corp
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Filing: 1972-05-30
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Granted: 1973-07-31
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Expires: 1992-05-30
Abstract
Abstract An image signal converter in the receiver of a facsimile system comprising a first memory for memorizing successive horizontal line signals contained in an image signal carried on a facsimile signal transmitted, and a second memory for consecutively memorizing the horizontal line signals by one field. The first memory is adapted to memorize the horizontal line signals reversely of the time base when the horizontal scanning direction in the sender is reversed and, on the other hand, the second memory is adapted to memorize the horizontal line signals in reverse order when the vertical scanning direction in the sender is reversed.
Inventors
- 👤 H Hayami
- 👤 R Kan
- 👤 M Kawabuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:20
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/00127; H04N1/00281; H04N1/00283; H04N1/00299; H04N1/32; H04N1/32358; H04N1/32363; H04N5/00; H04N5/76; H04N5/91; H04N7/00; H04N7/01; H04N7/0105; H04N7/011
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
287 words
An image signal converter in a receiver of a facsimile system, which comprises:: a demodulator for demodulating a facsimile signal carrying an image signal so as to separate said image signal from said facsimile signal, said image signal being produced through horizontally and vertically scanning an optical image and mixed with a synchronizing pulse train so that said image signal is constitutied by a plurality of successive horizontal line signals; a separator for separating said synchronizing pulse train from said image signal; a read-in pulse generator for producing read-in pulses in dependence on said synchronizing pulse train; a read-out pulse generator for producing read-out pulses; a memory circuit for memorizing said successive horizontal line signals and reading out the memorized horizontal line signals in response to said read-in and read-out pulses, said memory circuit including a timing controller for producing a start signal in response to said read-in or read-out pulses, an address indication pulse generator for producing an address indication pulses, a counting mode controller for producing an addition or subtraction mode signal, an address indication counter for counting said address indication pulses in addition mode when received said addition mode signal and in subtraction mode when received said subtraction mode signal and for producing an address indication signal when having counted a predetermined number of said address indication pulses, a memory driver for producing a memory drive signal when received both said start signal and said address indication signal, a memory for memorizing said horizontal line signals when received said memory drive signal and read-out means for reading out the memorized horizontal line signals when received said read-out pulses; and an endless recorder for successively recording the read-out horizontal line signals from said memory circuit.
Claim 2
Dependent Claim
287 words
An image signal converter in a receiver of a facsimile system, which comprises:: a demodulator for demodulating a facsimile signal carrying an image signal so as to separate said image signal from said facsimile signal, said image signal being produced through horizontally and vertically scanning an optical image and mixed with a synchronizing pulse train so that said image signal is constitutied by a plurality of successive horizontal line signals; a separator for separating said synchronizing pulse train from said image signal; a read-in pulse generator for producing read-in pulses in dependence on said synchronizing pulse train; a read-out pulse generator for producing read-out pulses; a memory circuit for memorizing said successive horizontal line signals and reading out the memorized horizontal line signals in response to said read-in and read-out pulses, said memory circuit including a timing controller for producing a start signal in response to said read-in or read-out pulses, an address indication pulse generator for producing an address indication pulses, a counting mode controller for producing an addition or subtraction mode signal, an address indication counter for counting said address indication pulses in addition mode when received said addition mode signal and in subtraction mode when received said subtraction mode signal and for producing an address indication signal when having counted a predetermined number of said address indication pulses, a memory driver for producing a memory drive signal when received both said start signal and said address indication signal, a memory for memorizing said horizontal line signals when received said memory drive signal and read-out means for reading out the memorized horizontal line signals when received said read-out pulses; and an endless recorder for successively recording the read-out horizontal line signals from said memory circuit.
Claim 3
Dependent Claim
248 words
An image signal converter as claimed in claim 1, in which said read-out pulse generator includes a horizontal and vertical synchronizing pulse signal generator for producing horizontal and vertical synchronizing pulse signals for said repeated video signal, a gate signal generating means for producing gate pulse signals each having a frequency equal to one-half of the repetition frequency of said synchronizing pulse train, said gate pulse signals being inverse in phase, one-half divider for one-half dividing said vertical synchronizing pulse signal, an inverter for inverting in phase the divided vertical synchronizing pulse signal, a first AND gate for passing therethrough said horizontal synchronizing pulse signal when received said divided vertical synchronizing pulse signal and one of said gate signals, a second AND gate for passing therethrough said horizontal synchronizing pulse signal when received the inverted and divided vertical synchronizing pulse signal and the other of said gate signals, an adder for adding the horizontal synchronizing pulse signals passed through said first and second AND gates, a first counter for counting said one of the gate signals in addition or subtraction mode, a second counter for counting the added horizontal synchronizing pulse signals, a coincident circuit for producing a coincident signal when the counted number of said first and second counter coincide with each other, a gate signal generator for producing an output gate signal in accordance with said synchronizing pulse train, and a third AND gate for passing therethrough said coincident signal when received said output gate signal.
Claim 4
Dependent Claim
55 words
An image signal converter as claimed in claim 2, in which said horizontal and vertical synchronizing pulse signal generator includes a disc of a video disc recorder, said vertical and horizontal synchronizing pulse signals being recorded on said disc, and a detector for detecting the vertical and horizontal synchronizing pulse signals recorded on said disc.
References Cited (Backward Citations)
US3601536A
Cited
US3603725A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |