Parity check logic for a code reading system

Claim 2

Parity control logic comprising: recirculating means for storing a plurality of data bits and for providing a cyclic memory signal which manifests the bits stored therein, selected ones of the data bits stored in said memory being manifested during a given portion of each cycle, said selected data bits including a size code which manifests a number related to the number of selected data bits manifested by said memory signal and at least one parity bit which causes a predetermined parity relationship to exist for said selected data bits; counter means for repetitiously counting between one and a certain number, said counter means having a count of one at the time said memory signal begins manifeSting said selected bits, said count being incremented after a fixed number of bits have been manifested by said memory signal; limit register means for being set to a count related to the number of said selected data bits manifested by said memory signal in response to the portion of said memory signal manifesting said size code; comparing means for providing a compare signal when the counts of said counter means and said limit register means are equal; control means for providing a control signal from the time said counter means contains a count of one until the occurrence of said comparing means signal; and parity checking means responsive to said memory signal and said control signal for determining whether said predetermined parity relationship exists.

Claim 3

The invention according to claim 1: wherein said bits stored in said memory means are divided into multibit characters; wherein said control means further includes logic means for providing a second control signal during the time said size code bits are manifested by said memory signal; wherein said limit register means includes means responsive to said second control signal for causing said signal manifesting said size code to be applied to said limit register means and for adjusting the count of said limit register means to reflect the number of characters in said selected data bits; and wherein said fixed number is equal to the number of data bits in one character.

Claim 4

The invention according to claim 1: wherein said bits stored in said memory means are divided into multibit characters numerically ordered so that during the first bit time of said given portion of each cycle, the first bit of the first character is manifested by said memory signal, said fixed number being equal to the number of bits in one character; wherein said control means further includes index register means, setting means for setting said index register means to a count equal to the numerical designation of the character having said size code, and second compare means for providing a second compare signal when the counts of said index register means and said counter means are equal, said index register means being responsive to said second compare signal for being reset to a count of zero; wherein said limit register means is responsive to said second compare signal and the bits of said then occurring memory signal for being set to a count equal to the number of characters in said selected data bits; wherein said setting means thereafter sets said index register means to a count of one, and said second compare means provides a third compare signal when the counts of said counter means and said index register means are equal; and wherein said control means further includes first control logic for providing said first mentioned control signal between the time said third compare signal occurs and said first mentioned compare signal occurs.

Claim 5

The invention according to claim 3: wherein said limit register means further includes means for adjusting the count of said limit register means to be equal to the number of characters of said selected data bits.

Claim 6

The invention according to claim 4: wherein said memory signal is a serial by bit signal; wherein each of said first, second and third compare signals occur for the time required for one character of bits to be manifested by said memory signal; and wherein said first control signal is provided from the beginning of said third compare signal until the end of said first compare signal.

Claim 7

The invention according to claim 5: wherein said parity checking means determines the parity relationship of that portion of said memory signal which is provided during the provision of said first control signal.

Claim 8

Parity checking logic for a data transfer system in which binary data is applied to a recirculating shift register memory one multibit character at a time in such a manner that successivEly applied characters are stored in correspondingly numbered memory locations, said binary data including a control information character and a certain number of information characters, said control character including a plurality of bits forming a size code which manifests a number related to said certain number, said binary data further including parity information which causes a preselected parity relationship to exist whenever the stored data is proper, said binary data being cyclically provided from said memory as a memory signal in the manifested order of said control information and thereafter said information characters, said parity checking logic comprising: position counter means for counting between one and at least a number equal to the maximum number of characters which can be stored in said memory, each character of said data being associated with one count of said position counter means and being provided a fixed time after said position counter reaches the count associated therewith, said control character being associated with a certain count of said position counter means; index register means for counting between zero and at least said number equal to the maximum number of characters which can be stored in said memory, the count of said index register means being incremented by one on command of a first control signal, limit register means capable of being set to a count equal to the number of multibit characters stored in said memory in response to the application thereto of a signal manifesting said size code; compare means for providing second and third control signals, said second control signal being provided whenever the counts of said position counter means and index register means are equal, said third control signal being provided whenever the counts of said limit register means and position counter means are equal; logic means for providing said first control signal to cause said index register means to be incremented to said certain count, for causing the size code portion of a signal manifesting said first control character to be applied to said limit register means in response to the provision of said second control signal, for resetting said index register to a count of zero, for providing said first control signal to cause said index register means to be incremented to a count of one, and for maintaining said next occurring second control signal provided until said third control signal occurs; and parity checking means for checking the parity of said binary data manifested from said memory signal during the time said next occurring second control signal is provided.

Claim 9

Parity checking logic for a data transfer system in which binary data is applied to a recirculating shift register memory one multibit character at a time in such a manner that successivEly applied characters are stored in correspondingly numbered memory locations, said binary data including a control information character and a certain number of information characters, said control character including a plurality of bits forming a size code which manifests a number related to said certain number, said binary data further including parity information which causes a preselected parity relationship to exist whenever the stored data is proper, said binary data being cyclically provided from said memory as a memory signal in the manifested order of said control information and thereafter said information characters, said parity checking logic comprising: position counter means for counting between one and at least a number equal to the maximum number of characters which can be stored in said memory, each character of said data being associated with one count of said position counter means and being provided a fixed time after said position counter reaches the count associated therewith, said control character being associated with a certain count of said position counter means; index register means for counting between zero and at least said number equal to the maximum number of characters which can be stored in said memory, the count of said index register means being incremented by one on command of a first control signal, limit register means capable of being set to a count equal to the number of multibit characters stored in said memory in response to the application thereto of a signal manifesting said size code; compare means for providing second and third control signals, said second control signal being provided whenever the counts of said position counter means and index register means are equal, said third control signal being provided whenever the counts of said limit register means and position counter means are equal; logic means for providing said first control signal to cause said index register means to be incremented to said certain count, for causing the size code portion of a signal manifesting said first control character to be applied to said limit register means in response to the provision of said second control signal, for resetting said index register to a count of zero, for providing said first control signal to cause said index register means to be incremented to a count of one, and for maintaining said next occurring second control signal provided until said third control signal occurs; and parity checking means for checking the parity of said binary data manifested from said memory signal during the time said next occurring second control signal is provided.

Claim 10

The invention according to claim 8: wherein said parity information includes a block check parity code and a modulo three parity code; wherein said parity check means includes block check means for checking the block check code parity of said information characters in response to the portion of said memory signal provided during said next occurring second control signal which manifests only said information characters and said block check code; and wherein said parity check means includes modulo three parity check means for checking the modulo three parity of said binary data in response to said memory signal provided during said next occurring second control signal.

Claim 11

The invention according to claim 8: wherein said binary data further includes a second control character which is manifested in said information signal after said information characters; wherein said third control signal is one character time long and said next occurring second control signal is provided until after said third control signal is provided; and wherein said block check means is inhibited from responding to said memory signal during the first character time of said next occurring second control signal and during the time said third control signal is provided.

Claim 12

The invention according to claim 9: wherein said limit registEr means includes control means responsive to said first occurring second control signal and said memory signal for providing a size code signal manifesting said size code, said size code signal being applied to a limit register which is further included in said limit register means for setting the count thereof to said size code number, said limit register means further including means for adjusting the count of said limit register to be equal to the number of data characters applied to said memory.