Circuit arrangement for baseline compensation

Claim 1

In a circuit arrangement for converting an electrical analogue input signal to an output signal, said input signal having peak components extending from a baseline component that is subject to variation in amplitude, an improved baseline correction arrangement comprising: An analogue-to-digital converter circuit for converting said input signal to digital pulses, the number of which correspond to variations in the amplitude of said input signal; a digital counter circuit having a plurality of stages for providing a plurality of digital output counts; a digital-to-analogue converter circuit coupled to said counter for converting said digital output counts to an analogue correction signal corresponding to said baseline component amplitude; means for applying said correction signal to said analogue-todigital converter to cancel said variations in amplitude of said baseline component of said input signal, said arrangement incorporating: a comparator circuit; means applying said baseline component signal to said comparator circuit; said comparator circuit providing an output signal when (a) said baseline component signal decreases and falls below a predetermined threshold value of one polarity, and (b) increases and exceeds a predetermined threshold value of an opposite polarity by being coupled to a bistable circuit having complementary outputs so that said bistable circuit exhibits one output when said baseline component signal increases and a complementary output when said baseline component signal decreases; reversible switching means for applying said correction signal to said analogue-to-digital converter and means for coupling said complementary outputs of said bistable circuit to actuate said switching means to determine the polarity of the correction signal that is applied to said analogue-to-digital converter; a coincidence gate; means for applying said output of said comparator circuit to an input of said coincidence gate, a pulse generator coupled to another input of said coincidence gate, means for coupling said coincidence gate to said digital counter circuit so that pulses from said pulse generator are applied to said digital counter circuit when said coincidence gate is activated; the output of said comparator circuit being adapted to be short circuited by means of a transistor switch during the occurrence of said peak components in said input signal to maintain said correction signal invariant during the occurrence of said peak components, said transistor switch being de-activated by a monostable flip-flop at the end of each peak component in said input signal and activated at the beginning of each peak component in said input signal; and said digital-to-analogue converter circuit including a plurality of resistors of different impedance values and a plurality of other switching means for coupling selected ones of said resistors in parallel between said counter and said converter means under the control of said counter stages so as to provide different analogue correction signals to said converter means depending upon the count in said digital counter.