Planar silicon gate mos process

Abstract

Abstract THIS INVENTION REFERS TO A METHOD OF MANUFACTURING A METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAV- ING A SOURCE, DRAIN AN CHANNEL REGION AND A GATE FORMED OVER THE CHANNEL REGION. THERE IS FORMED A FIRST INSULATING LAYER ON A SEMICONDUCTOR SUBSTRATE COVERING THE NON-ACITVE REGIONS OF THE TRANSISTOR AND THEN A SECOND INSULATING LAYER IS FORMED OVER THE ACTIVE REGION OF THE TRANSISTOR. A SEMICONDUCTIVE LAYER IS DEPOSITED OVER THE ACTIVE AND NON-ACTIVE REGIONS AND SUBSEQUENTLY THE GATE PERIPHERY OF THE SEMICONDUCTOR LAYER IS CONVERTED TO AN OXIDE WHICH IS SUBSEQUENTLY ETCHED AWAY THUS EXPOSING THE SOURCE AND DRAIN REGIONS OF THE TRANSISTOR AND THE REAMINDER OF THE GATE PERIPHERY TO THE SUBSTRATE SURFACE. THE GATE AND SOURCE AND DRAIN REGIONS ARE THEN DIFFUSED WITH A DOPING IMPURITY AND METAL CONTACTS ARE DEPOSITED TO THE SOURCE AND DRAIN REGIONS AND TO THE GATE SEMICONDUCTOR.

Inventors

• 👤 J Harlow
• 👤 R Swann
• 👤 J Penton
• 👤 M Bakker

Bibliographic Details