Amplitude stabilized l.c. oscillator with output circuits for producing semi-sinusoidal clock pulses

Claim 2

A clock-pulse generator arranged to produce a series of semisinusoidal clock pulses of the same polarity and of specified repetition frequency in a capacitive load, each said pulse being separated from the adjacent pulse by a predetermined interval of time, comprising an amplitude-stabilized self-oscillating sinewave oscillator including a resonating coil-and-capacitor circuit arranged to drive a pair of output circuits connected to said circuit and to output terminals of said oscillator in push-pull manner, each said output circuit being biased by a unidirectional potential derived from said oscillator and being arranged to suppress one-half of each sine wave thereby to supply a series of spaced, interlocking, unidirectional semi-sinusoids into an external capacitive load coupled to said output circuits.

Claim 3

The generator as claimed in claim 1 wherein said oscillator includes an oscillating active element, and wherein said resonating circuit comprises a transformer having a primary winding, a secondary winding and a tertiary winding, said primary winding being coupled to one electrode of said oscillating active element, said tertiary winding being coupled to a second electrode of said element in positive feedback relationship, said secondary winding being tuned capacitively to said specified frequency and having a center tap operatively coupled to said output circuits for enabling said output circuits to be coupled directly to its outer terminals.

Claim 4

The generator as claimed in claim 2 wherein said oscillator includes also an amplitude-stabilizing circuit comprising a zener diode and a transistor arranged to compare the voltage swing of said oscillator with the zener voltage of said diode, and to generate correcting pulses for reducing the amplitude of said oscillator when the swing exceeds a predetermined value.

Claim 5

The generator as claimed in claim 3 further comprising a peak detector arranged to rectify the voltage swing of said oscillator and means to couple the unidirectional output voltage so obtained to said output circuits as bias therefore via the center tap of said secondary winding.

Claim 6

The generator as claimed in claim 1 wherein each of said output circuits comprises a pair of similarly-directed diodes connected together at one electrode thereof and to the respective output of said oscillator to suppress one half-cycle of the output wave, and connected together at the other electrode thereof via the base-emitter path of a first transistor operating as an emitter-follower for discharging a load connected to said first transistor; and a complementary transistor connected base-collector across the collector-base path of said first transistor to act as a current source for charging such a load from said oscillator output; and a regulating resistor in circuit with said Second transistor.

Claim 7

A clock-pulse generator arranged to produce a series of semi-sinusoidal clock pulses of the same polarity having a predetermined basic repetition frequency with the pulses thereof spaced from one another by a predetermined time duration, for use with substantially capacitive loads, comprising a Hartley type oscillator circuit amplitude-stabilized by means of a stabilization circuit consisting of a comparison circuit including a zener diode and a transistor as coupling element, said oscillator comprising a resonant circuit consisting of a ferrite-cored transformer having a primary winding tapped near one end to provide a feedback winding, and a secondary winding capacitively tuned to the required frequency; said secondary winding being also center-tapped to provide a pair of output windings arranged to operate in push-pull manner to two output circuits; a rectifier circuit arranged to rectify a portion of the voltage of said oscillator so as to provide a unidirectional bias for said output circuits; and wherein said output circuits each comprise an arrangement of two diodes and a pair of complementary transistors so connected as to charge a capacitive load connected to said output circuits on one half-cycle of said oscillator output and to suppress the alternate half-cycle, whereby the two output circuits cooperate to produce interlocking semi-sinusoidal outputs having the desired clock-pulse waveform.

Claim 8

A clock-pulse generator arranged to produce a series of semi-sinusoidal clock pulses of the same polarity having a predetermined basic repetition frequency with the pulses thereof spaced from one another by a predetermined time duration, for use with substantially capacitive loads, comprising a Hartley type oscillator circuit amplitude-stabilized by means of a stabilization circuit consisting of a comparison circuit including a zener diode and a transistor as coupling element, said oscillator comprising a resonant circuit consisting of a ferrite-cored transformer having a primary winding tapped near one end to provide a feedback winding, and a secondary winding capacitively tuned to the required frequency; said secondary winding being also center-tapped to provide a pair of output windings arranged to operate in push-pull manner to two output circuits; a rectifier circuit arranged to rectify a portion of the voltage of said oscillator so as to provide a unidirectional bias for said output circuits; and wherein said output circuits each comprise an arrangement of two diodes and a pair of complementary transistors so connected as to charge a capacitive load connected to said output circuits on one half-cycle of said oscillator output and to suppress the alternate half-cycle, whereby the two output circuits cooperate to produce interlocking semi-sinusoidal outputs having the desired clock-pulse waveform.