US3762038A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thermal displays using air isolated integrated circuits and methods of making same
Assignee: Texas Instruments Inc
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Filing: 1970-09-09
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Granted: 1973-10-02
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Expires: 1990-09-09
Abstract
Abstract Thermal display including an air-isolated integrated semiconductor circuit having a semiconductor heating element array joined by a metallic connecting pattern which expands out over the heating elements to interconnect selected ones of them and form bonding pads. The thermally sensitive material on which a dynamic display is formed or on which a permanent display is printed is in direct contact with the monocrystalline semiconductor material of the heating element array. Circuit elements are formed within the monocrystalline semiconductor material of the heating element array and are mounted face down on a support having openings therein so that the metallic connecting pattern extends between the heating element array and the support to bonding pads which are exposed within the openings. Connections are made to the bonding pads through the openings to a metallized pattern on the underside of the support so that the connections are sufficiently displaced from the thermally sensitive display material. A parting agent is selectively located over the bonding pads prior to the mounting of the heating element array on the support to prevent the adhesive from covering the bonding pads and allow the connections to be made after the mounting of the heating element array on the support. The openings in the support also allow infrared alignment techniques to be utilized with an opaque support for air isolating the heater elements of the array and provide improved thermal as well as electrical isolation between the heater elements.
Inventors
- 👤 E Ruggiero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:05
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W20/00; H10W20/40; H10W72/00; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
173 words
A method of making an integrated semiconductor circuit comprising the steps of: forming a plurality of circuit elements adjacent one surface of a semiconductor wafer with an insulating layer on said one surface having openings therein exposing contact areas on said circuit elements, forming a conductive pattern on said insulating layer extending into said openings and interconnecting selected ones of said circuit elements and having a selected portion thereof lying on said insulating layer away from said circuit elements, said selected portion providing a bonding pad on said conductive pattern, selectively applying a parting agent substantially to said bonding pad only, mounting said semiconductor wafer on a solid support having an opening therein with an insulating adhesive so that said one surface of said semiconductor wafer is adjacent said support and said parting agent and said bonding pad is aligned with said opening, removing said parting agent to leave said bonding pad of said conductive pattern exposed and attaching an electrical connection to said bonding pad of said conductive pattern through said opening.
Claim 2
Independent Claim
173 words
A method of making an integrated semiconductor circuit comprising the steps of: forming a plurality of circuit elements adjacent one surface of a semiconductor wafer with an insulating layer on said one surface having openings therein exposing contact areas on said circuit elements, forming a conductive pattern on said insulating layer extending into said openings and interconnecting selected ones of said circuit elements and having a selected portion thereof lying on said insulating layer away from said circuit elements, said selected portion providing a bonding pad on said conductive pattern, selectively applying a parting agent substantially to said bonding pad only, mounting said semiconductor wafer on a solid support having an opening therein with an insulating adhesive so that said one surface of said semiconductor wafer is adjacent said support and said parting agent and said bonding pad is aligned with said opening, removing said parting agent to leave said bonding pad of said conductive pattern exposed and attaching an electrical connection to said bonding pad of said conductive pattern through said opening.
Claim 3
Dependent Claim
34 words
A method according to claim 1, wherein said support is insulating and comprises a conductor attached to its opposite surface near said opening including the step of attaching said electrical connection to said conductor.
Claim 4
Dependent Claim
34 words
A method according to claim 1, including the step of removing semiconductor material from said semiconductor wafer from one surface of said semiconductor wafer opposite said one surface to physically separate said circuit elements.
Claim 5
Dependent Claim
181 words
A method according to claim 3, including the steps of: forming a first opaque marker on said insulating layer near said portion of said conductive pattern, aligning said marker with said opening in said support semiconductor the mounting of said semiconductor wafer on said support, and wherein said step of removing semiconductor material from said semiconductor wafer comprises applying a photoresist layer on said opposite surface of said semiconductor wafer, applying a photomask above said photoresist layer to define the desired exposure pattern on said photoresist layer, said photomask having a second opaque marker thereon corresponding to said first opaque marker, shining infrared light through said opening in said support, detecting the infrared light pattern passing through the semiconductor wafer to determine the alignment between said first and second markers, adjusting the position of said photomask until said first and second markers align with each other, exposing said photoresist layer through said photomask to define the desired pattern on said photoresist layer, and removing selected portions of said photoresist layer to expose portions of said semiconductor material desired to be removed.
Claim 6
Independent Claim
236 words
A method of fabricating an integrated semiconductor circuit comprising the steps of: forming a plurality of circuit elements adjacent one surface of a semiconductor wafer wiTh an insulating layer over said one surface having openings therein exposing contact areas on said circuit elements, forming a conductive pattern on said insulating layer extending into said openings interconnecting selected ones of said circuit elements and said conductive pattern having at least one portion on said insulating layer away from said circuit elements, forming a first opaque marker on said insulating layer near said at least one portion, mounting said semiconductor wafer on an opaque support having a first opening therein with an insulating adhesive attaching said one surface to said support with said first marker and said at least one portion aligned with said first opening, applying a photoresist layer having a second opaque marker thereon over said photoresist layer, shining infrared light through said first opening in said support, detecting the infrared light pattern passing through said semiconductor wafer to determine the alignment of said first and second markers, adjusting the position of said photomask until said first and second markers are in alignment, exposing said photoresist layer through said photomask to define the desired pattern on said photoresist layer, selectively removing portions of said photoresist layer to leave semiconductor material between said circuit elements exposed, and removing the exposed semiconductor material to separate said circuit elements.
Claim 7
Independent Claim
236 words
A method of fabricating an integrated semiconductor circuit comprising the steps of: forming a plurality of circuit elements adjacent one surface of a semiconductor wafer wiTh an insulating layer over said one surface having openings therein exposing contact areas on said circuit elements, forming a conductive pattern on said insulating layer extending into said openings interconnecting selected ones of said circuit elements and said conductive pattern having at least one portion on said insulating layer away from said circuit elements, forming a first opaque marker on said insulating layer near said at least one portion, mounting said semiconductor wafer on an opaque support having a first opening therein with an insulating adhesive attaching said one surface to said support with said first marker and said at least one portion aligned with said first opening, applying a photoresist layer having a second opaque marker thereon over said photoresist layer, shining infrared light through said first opening in said support, detecting the infrared light pattern passing through said semiconductor wafer to determine the alignment of said first and second markers, adjusting the position of said photomask until said first and second markers are in alignment, exposing said photoresist layer through said photomask to define the desired pattern on said photoresist layer, selectively removing portions of said photoresist layer to leave semiconductor material between said circuit elements exposed, and removing the exposed semiconductor material to separate said circuit elements.
Claim 8
Dependent Claim
11 words
A method according to claim 1 wherein said support is ceramic.
Claim 9
Dependent Claim
28 words
A method according to claim 1 wherein said adhesive is substantially non-wetting to said parting agent to thereby allow direct access to said parting agent through said opening.
Claim 10
Independent Claim
310 words
A method of making an integrated semiconductor circuit comprising the steps of: a. forming a plurality of circuit elements adjacent one surface of a semiconductor wafer with an insulating layer on said one surface having openings therein exposing contact areas on said circuit elements; b. forming a conductive pattern on said insulating layer extending into said openings and interconnecting selected ones of said circuit elements and having a portion thereof lying on said insulating layer away from said circuit elements; c. forming a first opaque marker on said insulating layer near said portion of said conductive pattern; d. mounting with an insulating adhesive said semiconductor wafer on a support having an opening therein such that said marker is aligned with said opening in said support so that said one surface is adjacent said support and said parting agent is aligned with said opening; e. removing said parting agent to leave said portion of said conductive pattern exposed; and f. removing semiconductor material from said semiconductor wafer from one surface of said semiconductor wafer opposite said one surface to physically separate said circuit elements, said step of removing comprising applying a photoresist layer on said opposite surface of said semiconductor wafer, applying a photomask above said photoresist layer to define the desired exposure pattern on said photoresist layer, said photomask having a second opaque marker thereon corresponding to said first opaque marker, shining infrared light through said opening in said support, detecting the infrared light passing through the semiconductor wafer to determine the alignment between said first and second markers, adjusting the position of said photomask until said first and second markers align with each other, exposing said photoresist layer through said photomask to define the desired pattern on said photoresist layer, and removing selected portions of said photoresist layer to expose portions of said semiconductor material desired to be removed.
Claim 11
Independent Claim
310 words
A method of making an integrated semiconductor circuit comprising the steps of: a. forming a plurality of circuit elements adjacent one surface of a semiconductor wafer with an insulating layer on said one surface having openings therein exposing contact areas on said circuit elements; b. forming a conductive pattern on said insulating layer extending into said openings and interconnecting selected ones of said circuit elements and having a portion thereof lying on said insulating layer away from said circuit elements; c. forming a first opaque marker on said insulating layer near said portion of said conductive pattern; d. mounting with an insulating adhesive said semiconductor wafer on a support having an opening therein such that said marker is aligned with said opening in said support so that said one surface is adjacent said support and said parting agent is aligned with said opening; e. removing said parting agent to leave said portion of said conductive pattern exposed; and f. removing semiconductor material from said semiconductor wafer from one surface of said semiconductor wafer opposite said one surface to physically separate said circuit elements, said step of removing comprising applying a photoresist layer on said opposite surface of said semiconductor wafer, applying a photomask above said photoresist layer to define the desired exposure pattern on said photoresist layer, said photomask having a second opaque marker thereon corresponding to said first opaque marker, shining infrared light through said opening in said support, detecting the infrared light passing through the semiconductor wafer to determine the alignment between said first and second markers, adjusting the position of said photomask until said first and second markers align with each other, exposing said photoresist layer through said photomask to define the desired pattern on said photoresist layer, and removing selected portions of said photoresist layer to expose portions of said semiconductor material desired to be removed.
References Cited (Backward Citations)
US3508325A
Cited
US3542550A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |