Accurate monostable multivibrator

Claim 2

A circuit for generating a delayed signal comprising: a resistor and a capacitor connected to provide a two-terminal resistance-capacitance charging network; a source of direct voltage; an output circuit; connections from said source across the terminals of said network for charging said capacitor in one direction from a given low voltage to a predetermined voltage; means responsive to the charging of said capacitor to a predetermined voltage level for reversing said connections across the terminals of said network whereby said capacitor is discharged in the opposite direction, the charging and discharging of said capacitor both being through said resistor; connections from said source to said output circuit; and means responsive to the successive charging and discharging of said capacitor to said predetermined voltage for altering said connections from said source to said output circuit to generate said delayed signal.

Claim 3

The invention as defined in claim 1, and a clamping diode connected between said voltage source and the junction of said resistor and capacitor, said diode being poled to oppose conduction from said source to said junction.

Claim 4

A delay circuit for generating a signal after a time delay, said circuit comprising: a two-terminal resistance-capacitance charging network having first and second terminals, said network comprising a resistor and a capacitor connected in series between said terminals; a two-terminal voltage source having first and second terminals; first, second, third and fourth electronic switches each having first and second input terminals and an output terminal, each of said electronic switches having first and second operating states, the first state providing a connection from its output terminal to the first terminal of said source, the second state providing a connection from its output terminal to the second terminal of said source, said electronic switches being in said first state except when a given voltage level is present at both of said input terminals, said first electronic switch being initially in its first operating state; means connecting the first and second terminals of said network to the input terminals of said first and second electronic switches, respectively; a connection from the output terminal of the first electronic switch to the second input terminal of the second electronic switch, whereby said second electronic switch is initially in a second operating state; a connection from the junction of said resistor and capacitor to the first input terminal of said first electronic switch, the second input terminal of the first electronic switch being connected to the second terminal of said source; a connection between the output terminal of said third electronic switch and the first input terminal of said second electronic switch; a connection from the output terminal of the second electronic switch to the first input terminal of said third electronic switch; a second two-terminal resistance-capacitance charging network including a second resistor and a second capacitor connected in series between its terminals, one of said terminals being connected to the output terminal of said second electronic switch, the other of said terminals being connected to the second terminal of said source; a connection from the junction of said second resistor and said second capacitor to the first input terminal of said fourth electronic switch, said second input terminal of said fourth electronic switch being connected to the second terminal of said source; a connection from the output terminal of said fourth electronic switch to the second input terminal of said third electronic switch, whereby said third electronic switch is initially in its second operating state and said fourth electronic switch is initially in its first operating state; and a clamping diode connected between the junction of said capacitor and resistor and the first terminal of said source; said first electronic switch changing to its second operating state when said capacitor is charged to a predetermined level and said second switch is changed to its first operating state, whereby said network is charged in the opposite direction to said predetermined level, said third electronic switch changing to its second operating state when said capacitor is charged to said level in the opposite direction, said time delay signal being derived from the output terminal of said third electronic switch.

Claim 5

A delay circuit for generating a signal after a time delay, said circuit comprising: a two-terminal resistance-capacitance charging network having first and second terminals, said network comprising a resistor and a capacitor connected in series between said terminals; a two-terminal voltage source having first and second terminals; first, second, third and fourth electronic switches each having first and second input terminals and an output terminal, each of said electronic switches having first and second operating states, the first state providing a connection from its output terminal to the first terminal of said source, the second state providing a connection from its output terminal to the second terminal of said source, said electronic switches being in said first state except when a given voltage level is present at both of said input terminals, said first electronic switch being initially in its first operating state; means connecting the first and second terminals of said network to the input terminals of said first and second electronic switches, respectively; a connection from the output terminal of the first electronic switch to the second input terminal of the second electronic switch, whereby said second electronic switch is initially in a second operating state; a connection from the junction of said resistor and capacitor to the first input terminal of said first electronic switch, the second input terminal of the first electronic switch being connected to the second terminal of said source; a connection between the output terminal of said third electronic switch and the first input terminal of said second electronic switch; a connection from the output terminal of the second electronic switch to the first input terminal of said third electronic switch; a second two-terminal resistance-capacitance charging network including a second resistor and a second capacitor connected in series between its terminals, one of said terminals being connected to the output terminal of said second electronic switch, the other of said terminals being connected to the second terminal of said source; a connection from the junction of said second resistor and said second capacitor to the first input terminal of said fourth electronic switch, said second input terminal of said fourth electronic switch being connected to the second terminal of said source; a connection from the output terminal of said fourth electronic switch to the second input terminal of said third electronic switch, whereby said third electronic switch is initially in its second operating state and said fourth electronic switch is initially in its first operating state; and a clamping diode connected between the junction of said capacitor and resistor and the first terminal of said source; said first electronic switch changing to its second operating state when said capacitor is charged to a predetermined level and said second switch is changed to its first operating state, whereby said network is charged in the opposite direction to said predetermined level, said third electronic switch changing to its second operating state when said capacitor is charged to said level in the opposite direction, said time delay signal being derived from the output terminal of said third electronic switch.

Claim 6

The invention as defined in claim 3 wherein said second resistance-capacitance network is chargeable at a rate faster than the charging rate of said first resistance-capacitance network.

Claim 7

The invention as defined in claim 4 and a clamping diode connected between the output terminal of said third electronic switch and the first input terminal of said fourth electronic switch.

Claim 8

The invention as defined in claim 5 wherein each of said electronic switches is a NOR gate.

Claim 9

The invention as defined in claim 6 wherein said four NOR gates are comprised of a Complementary Metal Oxide Silicon integrated circuit.

Claim 10

The invention as defined in claim 5 wherein said first and third electronic switches are inverters.

Claim 11

A delay circuit for generating a signal after a time delay, said circuit comprising: a two-terminal resistance-capacitance charging network having first and second terminals, said network comprising a resistor and a capacitor connected in series between said terminals; a two-terminal voltage source having first and second terminals; first, second, and third electronic switches each having first and second input terminals and an output terminal, each of said electronic switches having first and second operating states, the first state providing a connection from its output terminal to the first terminal of said source, the second state providing a connection from its output terminal to the second terminal of said source, said electronic switches being in said first state except when a given voltage level is present at both of said input terminals, said first electronic switch being initially in its first operating state; means connecting the first and second terminals of said network to the output terminals of said first and second electronic switches, respectively; a connection from the output terminal of the first electronic switch to the second input terminal of the second electronic switch, whereby said second electronic switch is initially in a second operating state; a connection from the junction of said resistor and capacitor to the first input terminal of said first electronic switch, the second input terminal of the first electronic switch being connected to the second terminal of said source; a connection between the output terminal of said third electronic switch and the first input terminal of said second electronic switch; a connection from the output terminal of the second electronic switch to the first input termiNal of said third electronic switch, the second input terminal being connected to said second terminal of said source; a second two-terminal resistance-capacitance charging network including a second resistor and a second capacitor connected in series between its terminals, one of said terminals being connected to the output terminal of said second electronic switch, the other of said terminals being connected to the second terminal of said source; a connection from the junction of said second resistor and said second capacitor to the first input terminal of said third electronic switch, said second input terminal of said third electronic switch being connected to the second terminal of said source; and a clamping diode connected between the junction of said capacitor and resistor and the first terminal of said source; said first electronic switch changing to its second operating state when said capacitor is charged to a predetermined level and said second switch is changed to its first operating state, whereby said network is charged in the opposite direction to said predetermined level, said third electronic switch changing to its second operating state when said capacitor is charged to said level in the opposite direction, said time delay signal being derived from the output terminal of said third electronic switch.

Claim 12

A delay circuit for generating a signal after a time delay, said circuit comprising: a two-terminal resistance-capacitance charging network having first and second terminals, said network comprising a resistor and a capacitor connected in series between said terminals; a two-terminal voltage source having first and second terminals; first, second, and third electronic switches each having first and second input terminals and an output terminal, each of said electronic switches having first and second operating states, the first state providing a connection from its output terminal to the first terminal of said source, the second state providing a connection from its output terminal to the second terminal of said source, said electronic switches being in said first state except when a given voltage level is present at both of said input terminals, said first electronic switch being initially in its first operating state; means connecting the first and second terminals of said network to the output terminals of said first and second electronic switches, respectively; a connection from the output terminal of the first electronic switch to the second input terminal of the second electronic switch, whereby said second electronic switch is initially in a second operating state; a connection from the junction of said resistor and capacitor to the first input terminal of said first electronic switch, the second input terminal of the first electronic switch being connected to the second terminal of said source; a connection between the output terminal of said third electronic switch and the first input terminal of said second electronic switch; a connection from the output terminal of the second electronic switch to the first input termiNal of said third electronic switch, the second input terminal being connected to said second terminal of said source; a second two-terminal resistance-capacitance charging network including a second resistor and a second capacitor connected in series between its terminals, one of said terminals being connected to the output terminal of said second electronic switch, the other of said terminals being connected to the second terminal of said source; a connection from the junction of said second resistor and said second capacitor to the first input terminal of said third electronic switch, said second input terminal of said third electronic switch being connected to the second terminal of said source; and a clamping diode connected between the junction of said capacitor and resistor and the first terminal of said source; said first electronic switch changing to its second operating state when said capacitor is charged to a predetermined level and said second switch is changed to its first operating state, whereby said network is charged in the opposite direction to said predetermined level, said third electronic switch changing to its second operating state when said capacitor is charged to said level in the opposite direction, said time delay signal being derived from the output terminal of said third electronic switch.

Claim 13

The invention as defined in claim 9 wherein said second resistance-capacitance network is chargeable at a rate faster than the charging rate of said first resistance-capacitance network.

Claim 14

The invention as defined in claim 10 and a clamping diode connected between the output terminal of said third electronic switch and the first input terminal of said fourth electronic switch.

Claim 15

The invention as defined in claim 11 wherein each of said electronic swithces is a NAND gate.

Claim 16

The invention as defined in claim 12 wherein said four NAND gates are comprised of a Complementary Metal Oxide Silicon integrated circuit.

Claim 17

The invention as defined in claim 12, and a fourth electronic switch having first and second input terminals and first and second output terminals, said first output terminal being connected to the one terminal of said source only when said predetermined voltage level is applied to both of said input terminals, said second output terminal being connected to said other terminal of said source only when both of said predetermined voltage levels are not applied to both of said input terminals; a connection from the first input terminal to said one terminal of said source; and a connection from the output terminal of said third electronic switch to the second input terminal of said fourth electronic switch.

Claim 18

The invention as defined in claim 14 wherein said fourth electronic switch is a NAND gate.

Claim 19

The invention as defined in claim 14 wherein said first and fourth electronic switches are inverters.