Solid-state switching capacitor

Claim 2

An arrangement comprising: first and second terminal means for applying a bias voltage to said arrangement; a pair of capacitors each having one terminal in series with a respective unidirectional conducting device, and the series arrangements being coupled across a common resistor, said unidirectional devices being oppositely poled and coupling said capacitors to one of said first and second terminal means, the other terminals of said capacitors being coupled through a common tunneling capacitor to the other of said first and second terminal means, said tunneling capacitor having a multilayer metal-insulator-metal structure, said insulator layer being sufficiently thin to permit substantial conduction current to pass therethrough through the process of quantum mechanical tunneling upon application of a bias voltage between said first and second terminal means which is of insufficient magnitude to cause destruction of said insulator layer.

Claim 3

The arrangement of claim 1, wherein said insulator layer is of the order of 50 angstroms thick.

Claim 4

The arrangement of claim 1, wherein said common tunneling capacitor comprises a first layer of Al, a second layer of Al2O3 on said first layer, And a third layer of Al on said second layer; and said pair of capacitors comprises a pair of forth layers of Al2O3 on said first layer of Al, and a pair of fifth electrode layers of Al on said pair of forth layers, whereby said pair of capacitors and said common tunneling capacitor form a unitary structure.

Claim 5

A voltage-variable capacitance arrangement comprising: first and second terminal means for applying a bias voltage to said arrangement; a pair of tunneling capacitors each having one terminal in series with a respective unidirectional conducting device, said unidirectional devices being oppositely poled and coupled said capacitors to one of said first and second terminal means; the other terminals of said tunneling capacitors being coupled through a common capacitor to the other of said first and second terminal means, and a resistance means being coupled in parallel to said common capacitor; said tunneling capacitors each having a multilayer metal-insulator-metal structure, said insulating layer being sufficiently thin to permit substantual conduction current to pass therethrough through the process of quantum mechanical tunneling upon application of a bias voltage between said first and second terminal means which is of insufficient magnitude to cause destruction of said insulator layer.

Claim 6

A voltage-variable capacitance arrangement comprising: first and second terminal means for applying a bias voltage to said arrangement; a pair of tunneling capacitors each having one terminal in series with a respective unidirectional conducting device, said unidirectional devices being oppositely poled and coupled said capacitors to one of said first and second terminal means; the other terminals of said tunneling capacitors being coupled through a common capacitor to the other of said first and second terminal means, and a resistance means being coupled in parallel to said common capacitor; said tunneling capacitors each having a multilayer metal-insulator-metal structure, said insulating layer being sufficiently thin to permit substantual conduction current to pass therethrough through the process of quantum mechanical tunneling upon application of a bias voltage between said first and second terminal means which is of insufficient magnitude to cause destruction of said insulator layer.

Claim 7

The arrangement of claim 4, wherein the insulator layer of each of said tunneling capacitors is of the order of 50 angstroms thick.

Claim 8

The arrangement of claim 4, wherein the metal layers of the tunneling capacitors are such that the difference in workfunctions of the two metal layers of one tunneling capacitor is not equal to the corresponding difference for the other capacitor, whereby the threshold voltages for tunneling conduction for the two tunneling capacitors differ.

Claim 9

The arrangement of claim 4, wherein said common capacitor comprises a first layer of Al, a second layer of Al2O3 on said first layer, and a third layer of Al on said second layer; and, said tunneling capacitors each comprise a first tunneling layer of Al2O3 on said first layer of Al, and a second electrode layer of Al on said first tunneling layer, whereby said common capacitor and said tunneling capacitors form a unitary structure.

Claim 10

An arrangement comprising: first and second terminal means for applying a bias voltage to said arrangement, first and second tunneling capacitors each having one terminal connected to one of said first and second terminal means, the other terminals of said first and second tunneling capacitors being coupled through respective first and second capacitors to the other of said first and second terminal means, and first and second resistance means being coupled in parallel with said first and second capacitors, respectively, said first and second tunneling capacitors each comprising a multilayer metal-insulator-metal structure, said insulator layer being sufficiently thin to permit substantial conduction current to pass therethrough through the process of quantum mechanical tunneling upon application of a bias voltage between said first and second terminal means which is insufficient in magnitude to cause destruction of said insulator layer.

Claim 11

An arrangement comprising: first and second terminal means for applying a bias voltage to said arrangement, first and second tunneling capacitors each having one terminal connected to one of said first and second terminal means, the other terminals of said first and second tunneling capacitors being coupled through respective first and second capacitors to the other of said first and second terminal means, and first and second resistance means being coupled in parallel with said first and second capacitors, respectively, said first and second tunneling capacitors each comprising a multilayer metal-insulator-metal structure, said insulator layer being sufficiently thin to permit substantial conduction current to pass therethrough through the process of quantum mechanical tunneling upon application of a bias voltage between said first and second terminal means which is insufficient in magnitude to cause destruction of said insulator layer.

Claim 12

The arrangement of claim 8, wherein the insulator layer of each of said tunneling cacapacitors is of the order of 50 angstroms thick.

Claim 13

The arrangement of claim 8, wherein the difference in workfunction of the metal layers of said first tunneling capacitor is greater than the difference in workfunction of the metal layers of said second tunneling capacitor, whereby the threshold voltages for tunneling conduction for the two tunneling capacitors differ.