Gate-diffusion isolation for jfet depletion-mode bucket brigade circuit

Claim 2

A monolithic integrated circuit of the bucket-brigade type utilizing depletion-mode field-effect transistors of the p-n junction type (JFET) and comprising a common substrate fabricated of a material selected from the group consisting of an electrically insulating material and a lightly doped semiconductor material of a first conductivity type, an epitaxial layer of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layer, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect tansistors coupled longitudinally in series circuit relationship through the epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a plurality of spaced-apart heavily doped second semiconductor regions of the first conductivity type diffused in the epitaxial layer between the first semiconductor diffused regions to form the gate electrode regions therein so that the transistors are of the JFET type, the gate electrode regions being isolated from said substrate and from each other, a thin dielectric layer formed over said epitaxial layer and in contact therewith and provided with holes therethrough aligned with the gate electrode regions located in the epitaxial layer between the source and drain electrodes of each transistor, a plurality of narrowly spaced-apart metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the first doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a single row of a plurality of serially connected bucket-brigade stages in monolithic integrated circuit form, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucketbrigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and heavily doped third semiconductor regions of the first conductivity type diffused only partially through the thickness of the epitaxial layer and disposed only along two opposite sides of the series coupled source-to-drain transistor channels and capacitor storage sites and slightly spaced therefroM, said third semiconductor diffused regions adapted to be connected to a voltage source for reverse bias of said third semiconductor diffused regions resulting in formation of depletion regions in the epitaxial layer extending vertically to the substrate, the heavily doped third semiconductor diffused regions each being slightly spaced from said second semiconductor diffused regions to prevent merging thereof, the spacing not being sufficiently large to prevent lateral merging of the resultant depletion regions upon application of the clock pulse voltage to the second semiconductor diffused regions, the formation of the vertical depletion regions, extending from the third semiconductor regions to the substrate and the formation of the lateral depletion regions which merge the second semiconductor regions with the third semiconductor regions thereby defining the two side boundaries of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and prevent any undesired coupling of the charge packets at any time and to increase the transconductance of the transistors and to increase the packing density for a given area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET devices.

Claim 3

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said common substrate comprises a p conductivity type semiconductor material, said epitaxial layer comprises an n conductivity type semiconductor material, said heavily doped first semiconductor regions comprise an n conductivity type semiconductor material, and said heavily doped second and third semiconductor regions comprise a p conductivity type semiconductor material.

Claim 4

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said heavily doped third semiconductor regions are oriented parallel to each other and are overlapped by said metal layers in an orientation substantially perpendicular thereto.

Claim 5

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said epitaxial layer is a common layer in contact with the entire major surface of said substrate.

Claim 6

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said epitaxial layer comprises an n conductivity type semiconductor material and has a resistivity in the range of 0.2 to 3.0 ohm-cm.

Claim 7

The monolithic integrated bucket-brigade circuit set forth in claim 5 wherein the spacing between said second and third semiconductor diffused regions for an epitaxial layer resistivity of 1.0 ohm-cm. is in the range of 0.5 to 6.0 microns.

Claim 8

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein the thickness of the epitaxial layer is in the range of 1 to 7 microns and is determined primarily by the depth to which said second semiconductor regions are diffused therein.

Claim 9

A monolithic integrated circuit of the bucket-brigade type utilizing depletion-mode field-effect transistors of the p-n junction type (JFET) and comprising a common substrate fabricated of a material selected from the group consisting of an electrically insulating or lightly doped semiconductor material of a first conductivity type, an epitaxial layer of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layer and arranged in juxtaposed parallel oriented rows, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect transistors coupled longitudinally iN series circuit relationship in each row thereof through the epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a plurality of spaced-apart heavily doped second semiconductor regions of the first conductivity type diffused in the epitaxial layer between the first semiconductor diffused regions to form gate electrode regions therein so that the transistors are of the JFET type, the gate electrode regions being isolated from said substrate and from each other, a thin dielectric layer formed over said epitaxial layer and in contact therewith and provided with holes therethrough aligned with the gate electrode regions located in the epitaxial layer between the source and drain electrodes of each transistor, a plurality of narrowly spaced-apart parallel metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers oriented substantially perpendicular to the rows of serially coupled transistors and having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the first doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a plurality of rows and columns of bucket-brigade stages in monolithic integrated circuit form, the bucket-brigade stages being serially connected in each row, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucket-brigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and heavily doped third semiconductor regions of the first conductivity type diffused only partially through the thickness of the epitaxial layer and disposed only along two opposite sides of each of the rows of series coupled source-to-drain transistor channels and capacitor storage sites and slightly spaced therefrom, said third semiconductor diffused regions adapted to be connected to a voltage source for reverse-bias of said third semiconductor diffused regions resulting in formation of depletion regions in the epitaxial layer extending to the substrate, the heavily doped third semiconductor diffused regions each being slightly spaced from said second semiconductor diffused regions to prevent merging thereof, the spacing not being sufficiently large to prevent lateral merging of the resultant depletion regions upon application of the clock pulse voltage to the second semiconductor diffused regions, the formation of the vertical depletion regions extending from the third semiconductor regions to the substrate and the formation of the lateral depletion regions which merge the second semiconductor regions with the third semiconductor regions thereby defining the two side boundaries of each row of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and preventing any undesired coupling of the charge packets at any time, and to increase the transconducdance of the transistors and to increase the packing density for a given Area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET devices.

Claim 10

A monolithic integrated circuit of the bucket-brigade type utilizing depletion-mode field-effect transistors of the p-n junction type (JFET) and comprising a common substrate fabricated of a material selected from the group consisting of an electrically insulating or lightly doped semiconductor material of a first conductivity type, an epitaxial layer of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layer and arranged in juxtaposed parallel oriented rows, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect transistors coupled longitudinally iN series circuit relationship in each row thereof through the epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a plurality of spaced-apart heavily doped second semiconductor regions of the first conductivity type diffused in the epitaxial layer between the first semiconductor diffused regions to form gate electrode regions therein so that the transistors are of the JFET type, the gate electrode regions being isolated from said substrate and from each other, a thin dielectric layer formed over said epitaxial layer and in contact therewith and provided with holes therethrough aligned with the gate electrode regions located in the epitaxial layer between the source and drain electrodes of each transistor, a plurality of narrowly spaced-apart parallel metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers oriented substantially perpendicular to the rows of serially coupled transistors and having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the first doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a plurality of rows and columns of bucket-brigade stages in monolithic integrated circuit form, the bucket-brigade stages being serially connected in each row, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucket-brigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and heavily doped third semiconductor regions of the first conductivity type diffused only partially through the thickness of the epitaxial layer and disposed only along two opposite sides of each of the rows of series coupled source-to-drain transistor channels and capacitor storage sites and slightly spaced therefrom, said third semiconductor diffused regions adapted to be connected to a voltage source for reverse-bias of said third semiconductor diffused regions resulting in formation of depletion regions in the epitaxial layer extending to the substrate, the heavily doped third semiconductor diffused regions each being slightly spaced from said second semiconductor diffused regions to prevent merging thereof, the spacing not being sufficiently large to prevent lateral merging of the resultant depletion regions upon application of the clock pulse voltage to the second semiconductor diffused regions, the formation of the vertical depletion regions extending from the third semiconductor regions to the substrate and the formation of the lateral depletion regions which merge the second semiconductor regions with the third semiconductor regions thereby defining the two side boundaries of each row of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and preventing any undesired coupling of the charge packets at any time, and to increase the transconducdance of the transistors and to increase the packing density for a given Area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET devices.

Claim 11

The monolithic integrated bucket-brigade circuit set forth in claim 8 wherein said common substrate comprises a p conductivity type semiconductor material, said epitaxial layer comprises an n conductivity type semiconductor material, said heavily doped first semiconductor regions comprise an n conductivity type semiconductor material, and said heavily doped second and third semiconductor regions comprise a p conductivity semiconductor material.

Claim 12

The monolithic integrated bucket-brigade circuit set forth in claim 8 wherein said heavily doped third semiconductor regions are oriented parallel to each other and are overlapped by said metal layers in an orientation substantially perpendicular thereto.

Claim 13

The monolithic integrated bucket-brigade circuit set forth in claim 8 wherein the substrate semiconductor material is silicon, the epitaxial layer material is silicon, and the dielectric layer material is silicon dioxide.

Claim 14

The monolithic integrated bucket-brigade circuit set forth in claim 11 wherein the metal layer material is aluminum.