Charge transfer solid state display

Claim 2

In a semiconductor charge transfer device solid state display wherein information in the form of minority carriers is read in via shift register action and the metal-insulator-semiconductor structure is biased to effect light emission by recombination, the improvement comprising a semiconcuctor substrate having major surfaces on opposite sides, a continuous p-n junction defined in said substrate in a plane parallel to said major surfaces, said substrate comprising a semiconductor material having good light emitting characteristics, and bias means operably connected to said structure for avalanching said juntion thereby substantiAlly increasing the amount of light emitted by said display.

Claim 3

A semiconductor charge display as set forth in claim 1 wherein said substrate comprises gallium-arsenide phosphide.

Claim 4

A semiconductor charge solid state display as set forth in claim 1 wherein said substrate is selected from the group consisting of gallium nitride, gallium phosphide, and gallium-aluminum-arsenide.

Claim 5

A solid state display comprising: a. a semiconductor substrate having major surfaces on opposite sides. Semiconductor material adjacent, one surface being of one conductivity type and semiconductor material adjacent the other surface of opposite conductivity type defining a continuous p-n junction in said substrate which lies in a plane substantially parallel to said surfaces, b. means for reverse biasing said p-n junction to near avalanche breakdown, c. a pocket of said opposite conductivity type material extending from said one surface and combined within material of said one conductivity type, d. a relatively thin insulating layer over said one surface and pocket of opposite conductivity type defining an aperture therethru exposing a surface region of said pocket, e. ohmic contact means extending through said aperture and contacting said pocket for entering data in the form of minority carriers, f. a plurality of elongated substantially parallel electrodes over said insulating layer spaced from said aperture to define a charge coupled device shift register, g. clocking means of one polarity operably connected to said electrodes for sequentially shifting said data into respective bits of such shift register, and h. bias means connected to said electrodes for applying a bias of polarity opposite said one polarity effective to force electrical charge stored in said bits away from said electrodes and toward said p-n junction, thereby avalanching or multiplying the minority carriers in the depletion region of said junction.

Claim 6

A solid state display comprising: a. a semiconductor substrate having major surfaces on opposite sides. Semiconductor material adjacent, one surface being of one conductivity type and semiconductor material adjacent the other surface of opposite conductivity type defining a continuous p-n junction in said substrate which lies in a plane substantially parallel to said surfaces, b. means for reverse biasing said p-n junction to near avalanche breakdown, c. a pocket of said opposite conductivity type material extending from said one surface and combined within material of said one conductivity type, d. a relatively thin insulating layer over said one surface and pocket of opposite conductivity type defining an aperture therethru exposing a surface region of said pocket, e. ohmic contact means extending through said aperture and contacting said pocket for entering data in the form of minority carriers, f. a plurality of elongated substantially parallel electrodes over said insulating layer spaced from said aperture to define a charge coupled device shift register, g. clocking means of one polarity operably connected to said electrodes for sequentially shifting said data into respective bits of such shift register, and h. bias means connected to said electrodes for applying a bias of polarity opposite said one polarity effective to force electrical charge stored in said bits away from said electrodes and toward said p-n junction, thereby avalanching or multiplying the minority carriers in the depletion region of said junction.

Claim 7

A display system as set forth in claim 4 wherein said substate comprises gallium arsenide phosphide.

Claim 8

A display system as set forth in claim 4 wherein said substrate is selected from the group consisting of gallium arsenide phosphide, gallium phosphide, gallium-aluminum-arsenide, and gallium nitride.

Claim 9

In a semiconductor charge transfer device solid state display wherein information in the form of minority carriers is read in via shift register action and the metal-insulator-semiconductor structure is biased to force minority carriers into the bulk of said semiconductor to effect light emission by recombination, the improvement comprising a semiconductor substrate having major surfaces on opposite sides, said substrate comprising a first body of silicon of one conductivity type and a second contiguous body of a semiconductor material of opposite conductivity type and which exhibits good light - emitting characteristics, defining a continuous hetero p-n junction in a plane of said substrate substantially parallel to said major surfaces, said silicon body disposed for effecting said semiconductor charge shift register; and means for reverse biasing said junction to near avalanche breakdown, thereby avalanching the minority carriers in the depletion region of said p-n junction.

Claim 10

In a semiconductor charge transfer device solid state display wherein information in the form of minority carriers is read in via shift register action and the metal-insulator-semiconductor structure is biased to force minority carriers into the bulk of said semiconductor to effect light emission by recombination, the improvement comprising a semiconductor substrate having major surfaces on opposite sides, said substrate comprising a first body of silicon of one conductivity type and a second contiguous body of a semiconductor material of opposite conductivity type and which exhibits good light - emitting characteristics, defining a continuous hetero p-n junction in a plane of said substrate substantially parallel to said major surfaces, said silicon body disposed for effecting said semiconductor charge shift register; and means for reverse biasing said junction to near avalanche breakdown, thereby avalanching the minority carriers in the depletion region of said p-n junction.

Claim 11

A display system as set forth in claim 7 wherein said second body comprises a direct energy gap semiconductor material.

Claim 12

A display system as set forth in claim 8 wherein said second body comprises gallium arsenide phosphide.

Claim 13

A display system as set forth in claim 7 wherein said second body is selected from the group consisting of gallium phosphide, gallium nitride and gallium-aluminum-arsenide.

Claim 14

A solid state display comprising: a. a semiconductor substrate having major surfaces on opposite sides, said substrate comprising a first body of silicon of one conductivity type and a second contiguous body of a semiconductor material of opposite conductivity type and which exhibits good light emitting characteristics, definIng a hetero p-n junction in a plane of said substrate substantially parallel to said major surfaces: b. a pocket of said opposite conductivity type extending from the exposed surface of said silicon and confined therein; c. a relatively thin insulating layer over said silicon and pocket of opposite conductivity type defining an aperture exposing a surface region of said pocket; d. ohmic contact means extending through said aperture and contacting said pocket for entering data in the form of minority carriers; e. a plurality of elongated substantially parallel electrodes over said insulating layer spaced from said aperture to define a charge-coupled device shift register; f. clocking means of one polarity for sequentially shifting said data into respective bits of said shift register; g. means for reverse biasing said p-n junction to near avalanche breakdown; and h. bias means connected to said electrodes for selectively applying a bias of opposite polarity effective to force minority carriers toward said p-n hunction.

Claim 15

A solid state display comprising: a. a semiconductor substrate having major surfaces on opposite sides, said substrate comprising a first body of silicon of one conductivity type and a second contiguous body of a semiconductor material of opposite conductivity type and which exhibits good light emitting characteristics, definIng a hetero p-n junction in a plane of said substrate substantially parallel to said major surfaces: b. a pocket of said opposite conductivity type extending from the exposed surface of said silicon and confined therein; c. a relatively thin insulating layer over said silicon and pocket of opposite conductivity type defining an aperture exposing a surface region of said pocket; d. ohmic contact means extending through said aperture and contacting said pocket for entering data in the form of minority carriers; e. a plurality of elongated substantially parallel electrodes over said insulating layer spaced from said aperture to define a charge-coupled device shift register; f. clocking means of one polarity for sequentially shifting said data into respective bits of said shift register; g. means for reverse biasing said p-n junction to near avalanche breakdown; and h. bias means connected to said electrodes for selectively applying a bias of opposite polarity effective to force minority carriers toward said p-n hunction.

Claim 16

A solid state display as set forth in claim 11 wherein said substrate comprises gallium-arsenide-phosphide.

Claim 17

A solid state display as set forth in claim 11 wherein said substrate is selected from the group consisting of gallium phosphide, gallium nitride, and gallium-aluminum-arsenide.