US3794970A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Storage access apparatus
Assignee: International Business Machines Corp
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Filing: 1972-11-24
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Granted: 1974-02-26
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Expires: 1992-11-24
Abstract
Abstract In a circuit for addressing a data store with an address having a portion identifying a character location having several byte locations and a portion identifying one of the bytes within the addressed character location, means is provided for addressing a number of bytes per character that is not an integral power of 2. The two address portions are used conventionally for addressing a first part of the store in which the number of byte positions for each character is an integral power of 2. A second part of the store holds the next byte position for each character and is addressed by the combination of a set of fixed address bits and the character portion of the address used for addressing the first part of the store.
Inventors
- 👤 K Pearson
- 👤 G Zook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:57
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/02; G09G1/06; G09G1/08; G09G1/10; G09G5/00; G09G5/22; G09G5/24; G11; G11C; G11C17/00; G11C17/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
Apparatus for addressing a storage system to access a multibyte character having a number of bytes that is not an integral power of 2, comprising, means providing a character address having a number of bit positions designated M and being restricted in range to a first part of said storage system such that M-N predetermined ones of said bit positions hold a unique entry for each character address in said range, where N designates a number of bit positions in the address and is less than M, means providing N predEtermined bits defining a second part of said storage system, and means responsive to said M bit character address to address a multi-byte location in said first part of said store and responsive to said N predetermined bits and to said M bits for addressing an additional byte location in said second part of said storage system for each character address.
Claim 2
Dependent Claim
151 words
Apparatus for addressing a storage system to access a multibyte character having a number of bytes that is not an integral power of 2, comprising, means providing a character address having a number of bit positions designated M and being restricted in range to a first part of said storage system such that M-N predetermined ones of said bit positions hold a unique entry for each character address in said range, where N designates a number of bit positions in the address and is less than M, means providing N predEtermined bits defining a second part of said storage system, and means responsive to said M bit character address to address a multi-byte location in said first part of said store and responsive to said N predetermined bits and to said M bits for addressing an additional byte location in said second part of said storage system for each character address.
Claim 3
Dependent Claim
76 words
The addressing apparatus of claim 1 wherein said storage system comprises a store having common addressing components for said first part and said second part, whereby accessing said first and second parts is a sequential operation, and wherein said apparatus includes means responsive to a signal identifying the completion of the operation of accessing said first part to respond to said N predetermined address bits and said M address bits to address said additional byte locations.
Claim 4
Dependent Claim
44 words
The apparatus of claim 1 including means providing an additional N predetermined bits defining a third part of said store, and means responsive to said M address bits and to said additioial predetermined bits to address a second additional byte location in said store.
Claim 5
Dependent Claim
84 words
The apparatus of claim 1 wherein said number of bytes per character is larger than 2N and each multi-byte location in said first part of said storage system holds 2N bytes, and wherein said apparatus further includes, means for shifting N of said character address bits from the position of said N predetermined bits and shifting N of character address bits into a position to address a byte within the multi-byte location defined by said predetermined bits and M-N of said character address bits.
Claim 6
Dependent Claim
50 words
The apparatus of claim 4 comprising means for shifting said M address bits N positions to form N bits for addressing an additional byte location within a group of 2N bytes and to form M-N bits for addressing said group of 2N bytes within said second part of said store.
Claim 7
Dependent Claim
29 words
The apparatus of claim 5 further including means providing a limited number of character addresses in the range of otherwise unused portions of said second part of said store.
Claim 8
Dependent Claim
46 words
The apparatus of claim 4 including means providing an address of N bits defining a byte to be addressed in a multi-byte location in the first part of said store and means for shifting said M bits for addressing with said N predetermined bits one byte.
Claim 9
Dependent Claim
83 words
The apparatus of claim 7 wherein said store accesses one byte at a time and said apparatus includes latch means connected to be set to one state for addressing a multi-byte location in said first part of said store and to be set to a different state in response to a predetermined bit in a byte read from said store, and means responsive to said different state of said latch means for operating said means for shifting for addressing an additional byte location.
Claim 10
Dependent Claim
78 words
The apparatus of claim 8 including means providing an additional N predetermined bits defining a third part of said store, and wherein said latch means includes a first latch connected to be set to a second state by an operation to read the last byte of a multi-byte location and a second latch connected to be set to a second state in response to an operation to read an additional byte in said second part of said store.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |