US3798607A
Expired / Lapsed
US
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Magnetic bubble computer
Assignee: Monsanto Co
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Filing: 1972-12-01
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Granted: 1974-03-19
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Expires: 1992-12-01
Abstract
Abstract In a general purpose computer system operating on a fetchexecute cycle, arithmetic, logic, storage and control functions are carried out by means of magnetic bubble circuits. A plurality of logic sub-systems called modules are interconnected by a closed unidirectional buss permitting intermodule transfer of data in the form of magnetic bubbles. The memory for the computer consists of a plurality of serial shift registers called marktime lines each comprising a chain of recirculating loops. On signal, data can be advanced in series around the chain. Modules in one subset are specialized to perform various functions. The remaining modules constitute logic interfaces between corresponding mark-time lines and the special subset of modules. All instructions include designating an intermodule transfer or of initiating a search for a storage location in a mark-time line.
Inventors
- 👤 R Minnick
- 👤 W Semon
- 👤 P Bailey
- 👤 R Sandfort
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F3/00; G06F3/007; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G11; G11C; G11C19/00; G11C19/02; G11C19/08; G11C19/0875; H; H03; H03K; H03K19/00; H03K19/02; H03K19/16; H03K19/168
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
60 words
A bubble circuit system, comprising a plurality of bubble logic modules for performing a plurality of operations in response to control signals, a closed bubble path interconnecting said modules for transmitting bubbles from one module to another and a central control unit separately connected with each one of said modules for selective operation thereof by means of said control signals.
Claim 2
Dependent Claim
60 words
A bubble circuit system, comprising a plurality of bubble logic modules for performing a plurality of operations in response to control signals, a closed bubble path interconnecting said modules for transmitting bubbles from one module to another and a central control unit separately connected with each one of said modules for selective operation thereof by means of said control signals.
Claim 3
Dependent Claim
48 words
The bubble circuit system of claim 1, wherein each module has means responsive to at least one of said control signals for passing incoming bubbles from said closed path through said module and back onto said closed path without change to serve a conduit function for said bubbles.
Claim 4
Dependent Claim
71 words
The bubble circuit system of claim 2, wherein at least two of said modules have read/write storage means oeprable by said control unit, and said control unit has means for causing one of said modules to read stored bubble bits out onto said closed path, another of said modules to write said bubble bits when received into said storage means, and the rest of said modules to serve said conduit function.
Claim 5
Dependent Claim
66 words
A bubble circuit arrangement, comprising a plurality of closed loops for circulating bubbles, a first closed bubble path interconnecting said closed loops, means for advancing bubbles from one loop to another via said first path, a second closed bubble path, and means selectively interconnecting one of said loops on said first path with said second path for transferring bubbles between said first and second bubble paths.
Claim 6
Dependent Claim
66 words
A bubble circuit arrangement, comprising a plurality of closed loops for circulating bubbles, a first closed bubble path interconnecting said closed loops, means for advancing bubbles from one loop to another via said first path, a second closed bubble path, and means selectively interconnecting one of said loops on said first path with said second path for transferring bubbles between said first and second bubble paths.
Claim 7
Dependent Claim
140 words
A bubble computer, comprising a plurality of bubble logic modules for performing a plurality of specified operations in response to control bubble bits, a closed bubble path interconnecting all of said modules in series, a bubble control unit, a plurality of control bubble paths between said control unit and corresponding ones of said modules, one subset of modules in which each module has at least one bubble register and means for writing incoming bubble bits into said register from said closed path and for reading out stored bubble bits onto said closed path, a second subset of modules in which each module has means for performing arithmetic operations on incoming data from said closed path, said control unit having means for causing said control bubble bits designating specific operations to be sent via said control bubble paths to said modules.
Claim 8
Dependent Claim
140 words
A bubble computer, comprising a plurality of bubble logic modules for performing a plurality of specified operations in response to control bubble bits, a closed bubble path interconnecting all of said modules in series, a bubble control unit, a plurality of control bubble paths between said control unit and corresponding ones of said modules, one subset of modules in which each module has at least one bubble register and means for writing incoming bubble bits into said register from said closed path and for reading out stored bubble bits onto said closed path, a second subset of modules in which each module has means for performing arithmetic operations on incoming data from said closed path, said control unit having means for causing said control bubble bits designating specific operations to be sent via said control bubble paths to said modules.
Claim 9
Dependent Claim
105 words
The computer of claim 5, wherein said control unit is adapted to operate said computer on a fetch-execute cycle and includes means for designating during the fetch phase one of said modules in said one subset as a source module and causing said source module to read an instruction out onto said closed path to an instruction register in a destination module in accordance with a command stored in one of said modules containing the address of said instruction, and means for sending control bubble bits during the execute cycle in accordance with the instruction in said instruction register to specified source and destination modules.
Claim 10
Dependent Claim
39 words
The computer of claim 6, wherein each of said modules has means for signalling said control unit via a respective control bubble path that bubble bits destined for that module have been received and said closed path is clear.
Claim 11
Dependent Claim
132 words
A bubble computer, comprising a plurality of bubble logic modules for performing specified operations in response to control bubble bits, a closed unidirectional bubble path interconnecting said modules in series, a bubble memory section including a plurality of serial bubble shift registers, a subset of said modules called line modules interfacing corresponding ones of said serial shift registers with said closed path, the remaining bubble performing a plurality of functions including arithmetical operations on incoming bubble bits on said closed path, a bubble control unit, a plurality of control bubble paths separately interconnecting all of said modules with said control unit, said control unit having means for sending control bubble bits to specified source and destination modules via said control bubble paths in accordance with an instruction from one of said modules.
Claim 12
Dependent Claim
132 words
A bubble computer, comprising a plurality of bubble logic modules for performing specified operations in response to control bubble bits, a closed unidirectional bubble path interconnecting said modules in series, a bubble memory section including a plurality of serial bubble shift registers, a subset of said modules called line modules interfacing corresponding ones of said serial shift registers with said closed path, the remaining bubble performing a plurality of functions including arithmetical operations on incoming bubble bits on said closed path, a bubble control unit, a plurality of control bubble paths separately interconnecting all of said modules with said control unit, said control unit having means for sending control bubble bits to specified source and destination modules via said control bubble paths in accordance with an instruction from one of said modules.
Claim 13
Dependent Claim
43 words
The computer of claim 8, wherein each said line module has means for performing a search for bubble bits stored at an address specified by an instruction in one of said modules in accordance with specific control bubble bits from said control unit.
Claim 14
Dependent Claim
133 words
The computer of claim 9, wherein said control unit operates said computer on a fetch-execute cycle, in which during the fetch phase of one of said line modules is designated as a source module from which an instruction is fetched and sent via said closed path to an instruction register in a destination module, and during the execute phase the instruction stored in said instruction register is used by said control unit to designate the operations of specified source and destination modules, all of said modules having means for signalling said control unit via respective ones of said control paths when bubble bits destined for that module have been received, said control unit changing from the fetch to the execute phase or vice versa in response to a signal from a destination module.
Claim 15
Dependent Claim
29 words
The computer of claim 10, wherein said line module has means for carrying out a designated search after signalling said control unit to switch back to the fetch phase.
Claim 16
Dependent Claim
64 words
The computer of claim 8, wherein each said serial shift register includes a plurality of closed loops for circulating bubbles, a plurality of normally deactivated interloop transfer paths between said loops for causing serial transfer of the bubbles in one loop to a succeeding loop in response to a shift signal, each said line module having means for generating said shift signal on command.
Claim 17
Dependent Claim
69 words
A bubble serial shift register, comprising a bubble shift circuit including a plurality of closed loops for circulating bubbles and a plurality of normally deactivated interloop transfer paths between successive ones of said loops for causing serial transfer of the bubbles in one loop to the next loop in response to a shift signal, and means operatively connected to said shift circuit for generating said shift signal on command.
Claim 18
Dependent Claim
69 words
A bubble serial shift register, comprising a bubble shift circuit including a plurality of closed loops for circulating bubbles and a plurality of normally deactivated interloop transfer paths between successive ones of said loops for causing serial transfer of the bubbles in one loop to the next loop in response to a shift signal, and means operatively connected to said shift circuit for generating said shift signal on command.
Claim 19
Dependent Claim
29 words
The shift register of claim 13, wherein the length of each interloop transfer path is sufficient to provide enough time for bubbles in said next loop to be extracted.
Claim 20
Dependent Claim
32 words
The shift register of claim 14, wherein each loop stores double data in the form of a word of specified length, the length of said transfer path corresponding to the word length.
Claim 21
Dependent Claim
31 words
The shift register of claim 13, wherein said shift signal generating means includes electrical conductor means arranged to magnetically influence bubble data in said loops to enter said transfer paths simultaneously.
Claim 22
Dependent Claim
72 words
The shift register of claim 16, wherein said closed loops and transfer paths are constructed of substantially similar circuit elements, each said transfer path having an entrance and an exit, said entrance to one of said transfer paths from one of said loops being formed by a branch off of said closed loop having means for excluding from said path bubbles circulating on said loop in the absence of said shift signal.
Claim 23
Dependent Claim
41 words
The shift register of claim 17, wherein said electrical conductor means includes a continuous conductor having a plurality of loops adjacent to corresponding entrances to said transfer paths for magnetically attracting bubbles in said closed loops onto said transfer paths simultaneously.
Claim 24
Dependent Claim
53 words
The shift register of claim 18, wherein at least one subset of said closed loops is arranged physically in series, with said transfer paths reversing direction once between adjacent closed loops such that the entrance and exit of each of said transfer paths is formed on corresponding adjacent sides of successive closed loops.
Claim 25
Dependent Claim
66 words
A bubble switching system, comprising flip-flop means for producing and ceasing to produce output bubbles in response to an input control bubble, and logic means responsive to said flip-flop means output having two input channels and an output channel for propagating bubbles corresponding to bubbles on one or the other of said input channels depending on the presence or absence of said flip-flop means output bubbles.
Claim 26
Dependent Claim
66 words
A bubble switching system, comprising flip-flop means for producing and ceasing to produce output bubbles in response to an input control bubble, and logic means responsive to said flip-flop means output having two input channels and an output channel for propagating bubbles corresponding to bubbles on one or the other of said input channels depending on the presence or absence of said flip-flop means output bubbles.
Claim 27
Dependent Claim
142 words
A bubble logic system for routing M sequential control bits to an address designated by N sequential address bits where M and N are integers, comprising serial-to-parallel control means having an input channel for receiving a bubble stream representing said N serial bits and having N output channels on said said address bits are produced in parallel, bubble multiplier means operatively receiving the outputs of said converter means and having N outpUt channels on each of which the corresponding bubble bit is reproduced in series M times, and decoding means having 2N parallel output and N parallel input channels for operatively receiving the outputs of said multiplier means and receiving said M sequential control bits for producing a serial output corresponding to said control bits on one of said 2N output channels corresponding to the address represented by said N address bits.
Claim 28
Dependent Claim
142 words
A bubble logic system for routing M sequential control bits to an address designated by N sequential address bits where M and N are integers, comprising serial-to-parallel control means having an input channel for receiving a bubble stream representing said N serial bits and having N output channels on said said address bits are produced in parallel, bubble multiplier means operatively receiving the outputs of said converter means and having N outpUt channels on each of which the corresponding bubble bit is reproduced in series M times, and decoding means having 2N parallel output and N parallel input channels for operatively receiving the outputs of said multiplier means and receiving said M sequential control bits for producing a serial output corresponding to said control bits on one of said 2N output channels corresponding to the address represented by said N address bits.
Claim 29
Dependent Claim
38 words
A bubble multiplying circuit, comprising means for producing a plurality of simultaneous bubble bit replicas corresponding to a single bubble bit input, and parallel-to-serial converter means for producing said bubble bit replicas in series on an output channel.
Claim 30
Dependent Claim
38 words
A bubble multiplying circuit, comprising means for producing a plurality of simultaneous bubble bit replicas corresponding to a single bubble bit input, and parallel-to-serial converter means for producing said bubble bit replicas in series on an output channel.
References Cited (Backward Citations)
US3541522A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-18 | 1977-09-17 | 1978-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-18 | 1981-09-17 | 1982-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-18 | 1985-09-17 | 1986-03-19 | $7700.00 | Window Closed / Lapsed |