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US3801737A Expired / Lapsed US ⏱️ 0.0 years remaining

Video signal compression and expansion system and devices therefor

Assignee: Ricoh Co Ltd
•
Filing: 1972-07-10
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Granted: 1974-04-02
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Expires: 1992-07-10
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Abstract

Abstract A video signal compression and expansion system characterized by comparing, bit by bit, the binary coded video signals of one scanning line derived by the scanning of a pattern with the reference binary coded video signals of the preceding line in such a manner that when the bit patterns coincide with each other, a first signal is generated but when they do not coincide with each other, a second signal is generated, transmitting no signal so long as said first signals follow in succession but transmitting a line address signal representing a scanning line containing said second signal and a bit position signal representing the bit position of said second signal only when said second signal is derived, reproducing the previously prepared binary coded video signals so long as said line address signal is not received, but reversing the bit in polarity at the bit position designated by said bit position signal when said line address signal is received and detected, and using thus obtained video signals as reference video signals for comparison with the video signals in the next scanning line.

Inventors

  • 👤 T Fukushima
  • 👤 M Ogawa
  • 👤 Y Komura
  • 👤 S Hirata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 07:53
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/417

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 201 words
A signal compression device comprising a. a first shift register for storing therein the binary coded video signals of a pattern along a line being scanned, a second shift register for storing therein the binary coded video signals derived by the scanning of the preceding line, b. a comparator for comparing, bit by bit, said two video signals in such a manner that when the video signals in the corresponding bit positions coincide with each other, a signal representing ''''0'''' may be generated but when they do not coincide with each other, a signal representing ''''1'''' may be generated, and c. a logic and control circuit for generating a group of signals consisting of a line address signal representing a scanning line containing said signals representing ''''1'''' and an address signal representing the bit position from which a group of said signals representing ''''1'''' appear in succession or said address signal representing the bit position from which a group of said signals representing ''''1'''' appear in succession and an address signal representing the bit position at which the last of said signals representing ''''1'''' in said group appears, depending upon the number of said signals representing ''''1'''' contained in said group.
Claim 2
Dependent Claim 201 words
A signal compression device comprising a. a first shift register for storing therein the binary coded video signals of a pattern along a line being scanned, a second shift register for storing therein the binary coded video signals derived by the scanning of the preceding line, b. a comparator for comparing, bit by bit, said two video signals in such a manner that when the video signals in the corresponding bit positions coincide with each other, a signal representing ''''0'''' may be generated but when they do not coincide with each other, a signal representing ''''1'''' may be generated, and c. a logic and control circuit for generating a group of signals consisting of a line address signal representing a scanning line containing said signals representing ''''1'''' and an address signal representing the bit position from which a group of said signals representing ''''1'''' appear in succession or said address signal representing the bit position from which a group of said signals representing ''''1'''' appear in succession and an address signal representing the bit position at which the last of said signals representing ''''1'''' in said group appears, depending upon the number of said signals representing ''''1'''' contained in said group.
Claim 3
Dependent Claim 152 words
A signal expansion device comprising a. a shift register for storing therein the binary coded video signals contained in the preceding scanning line, b. a register for storing therein a signal group consisting of an address signal representing the bit position from which a group of signals representing ''''1'''' appear in succession with or without an address signal representing the bit position at which the last of said signals representing ''''1'''' appears, and c. means for circulating the content in said shift register while transmitting on an output line said content as long as said signal group is not received in said register, and for reversing the bit pattern in polarity of said content in said shift register designated by said signal group when said signal group is received in said register and transmitting said content whose bit pattern has been reversed in polarity onto said output line while circulating the same.
Claim 4
Dependent Claim 152 words
A signal expansion device comprising a. a shift register for storing therein the binary coded video signals contained in the preceding scanning line, b. a register for storing therein a signal group consisting of an address signal representing the bit position from which a group of signals representing ''''1'''' appear in succession with or without an address signal representing the bit position at which the last of said signals representing ''''1'''' appears, and c. means for circulating the content in said shift register while transmitting on an output line said content as long as said signal group is not received in said register, and for reversing the bit pattern in polarity of said content in said shift register designated by said signal group when said signal group is received in said register and transmitting said content whose bit pattern has been reversed in polarity onto said output line while circulating the same.
Claim 5
Dependent Claim 314 words
Apparatus for compressing video signals representing successive binary coded video scan lines each identified by a Y-address, comprising: means for comparing each current scan line with the preceding scan line by comparing each pair of correspondingly positioned elemental areas of the two scan lines and for generating a first signal when a pair of compared elemental areas coincide and a second signal when a pair of compared elemental areas do not coincide to thereby generate a current delta signal line comprising the first and second signal resulting from the comparison of the current and the preceding scan lines by the comparing means; means for comparing the current and the preceding delta signal lines and for inhibiting the generation of output signals when the current delta signal line contains only first signals and the preceding delta signal line also contains only first signals, for generating as output signals a Mode A signal and the Y-address of the current scan line when the current delta signal line contains only first signals but the preceding delta signal line contains at least one second signal, and for generating as output signals a Mode B signal followed by the Y-address of the current scan line when the current delta signal line contains at least one second signal; means for generating as output signals following each Mode B signal an X-address representing the position of the fiRst of each set of one or more immediately adjacent second signals in the current delta signal line followed by each of the second signals of the set if the number of second signals in the set is less than a predetermined number; and means for generating as output signals a first X-address representing the start of a set of immediately adjacent second signals whose number is greater than said predetermined number and a second X-address representing the end of the last recited set.
Claim 6
Dependent Claim 314 words
Apparatus for compressing video signals representing successive binary coded video scan lines each identified by a Y-address, comprising: means for comparing each current scan line with the preceding scan line by comparing each pair of correspondingly positioned elemental areas of the two scan lines and for generating a first signal when a pair of compared elemental areas coincide and a second signal when a pair of compared elemental areas do not coincide to thereby generate a current delta signal line comprising the first and second signal resulting from the comparison of the current and the preceding scan lines by the comparing means; means for comparing the current and the preceding delta signal lines and for inhibiting the generation of output signals when the current delta signal line contains only first signals and the preceding delta signal line also contains only first signals, for generating as output signals a Mode A signal and the Y-address of the current scan line when the current delta signal line contains only first signals but the preceding delta signal line contains at least one second signal, and for generating as output signals a Mode B signal followed by the Y-address of the current scan line when the current delta signal line contains at least one second signal; means for generating as output signals following each Mode B signal an X-address representing the position of the fiRst of each set of one or more immediately adjacent second signals in the current delta signal line followed by each of the second signals of the set if the number of second signals in the set is less than a predetermined number; and means for generating as output signals a first X-address representing the start of a set of immediately adjacent second signals whose number is greater than said predetermined number and a second X-address representing the end of the last recited set.
Claim 7
Dependent Claim 34 words
Apparatus as in claim 3 wherein each of the scan lines is represented as a succession of binary bits, and wherein said first signals are binary zeros and said second signals are binary ones.
Claim 8
Dependent Claim 30 words
Apparatus as in claim 3 wherein the elemental areas compared by the scan line comparing means are correspondingly positioned binary bits of the two video scan lines which are compared.
Claim 9
Dependent Claim 60 words
Apparatus as in claim 3 including means for supplying to the scan line comparing means defined binary coded signals representing the nonexistent preceding scan line when the current scan line is the first of a succession of scan lines and for supplying to the delta signal line comparing means defined binary signals representing the nonexistent corresponding previous delta signal line.
Claim 10
Dependent Claim 35 words
Apparatus as in claim 6 wherein each of the video scan lines is represented by a succession of binary signals, and wherein said first signals are binary zeros and said second signals are binary ones.
Claim 11
Dependent Claim 31 words
Apparatus as in claim 7 wherein said elemental areas which are compared by the scan line comparing means are correspondingly positioned binary bits of the two scan lines which are compared.
Claim 12
Dependent Claim 77 words
Apparatus as in claim 3 wherein the scan line comparing means comprise a first shift register for storing the binary coded signals representing the current scan line, a second shift register receiving the output of the first register to store thereby the preceding scan line, and a comparator receiving the outputs of the first and the second shift registers to compare thereby the current and the preceding scan line and to generate a succession of delta signals.
Claim 13
Dependent Claim 204 words
Apparatus as in claim 9 wherein the delta signal line comparing means comprise a shift register for storing the delta signals output from the comparator, a first counter for storing the Y-address of the current scan line, a second counter for storing the X-address of the bit position currently compared by the comparator, a Mode A and B register storing a Mode A signal if the current delta signal line contains only first signals but the preceding delta signal line contained at least one second signal and storing a Mode B signal if the current line has at least one second signal, a buffer register, and a discriminator for inhibiting loading of the buffer register when both the preceding and the current delta signal lines contain only first signals, for loading into the buffer register the contents of the first counter and of the Mode A and B register when the preceding delta signal line contained at least one second signal but the current delta signal line contains only first signals, and for loading into the buffer register the contents of the first counter and of the Mode A and B register when the current delta signal line contains at least one second signal.
Claim 14
Dependent Claim 102 words
Apparatus as in claim 10 wherein the discriminator includes means for detecting the number of successive second signals in the current delta signal line and for loading into the buffer register the contents of the second counter and the successive second signals of a set of second signals which is shorter than a predetermined length and for loading into the buffer register the contents of the second counter at the start of a set of second signals which is longer than said predetermined length and the contents of the second counter at the end of the last recited set of second signals.
Claim 15
Dependent Claim 298 words
Method of compressing video signals representing successive binary coded video Scan lines each identified by a Y-address, comprising: comparing each current scan line with the preceding scan line by comparing each pair of correspondingly positioned elemental areas of the two scan lines and generating a first signal when a pair of compared elemental areas coincide and a second signal when a pair of compared elemental areas do not coincide to thereby generate a current delta signal line comprising the first and second signals resulting from the comparison of the current and the preceding scan lines; comparing the current and the preceding delta signal lines and inhibiting the generation of output signals when the current delta signal line contains only first signals and the preceding delta signal line also contains only first signals, generating as output signals a Mode A signal and the Y-address of the current scan line when the current delta signal line contains only first signals but the preceding delta signal line contains at least one second signal, and generating as output signals a Mode B signal followed by the Y-address of the current scan line when the current delta signal line contains at least one second signal; generating as output signals following each Mode B signal an X-address representing the positions of the first of each set of one or more immediately adjacent second signals in the current delta signal line followed by each of the second signals of the set if the number of second signals in the set is less than a predetermined number; and generating as output signals a first X-address representing the start of a set of immediately adjacent second signals whose number is greater than said predetermined number and a second X-address representing the end of the last recited set.
Claim 16
Dependent Claim 298 words
Method of compressing video signals representing successive binary coded video Scan lines each identified by a Y-address, comprising: comparing each current scan line with the preceding scan line by comparing each pair of correspondingly positioned elemental areas of the two scan lines and generating a first signal when a pair of compared elemental areas coincide and a second signal when a pair of compared elemental areas do not coincide to thereby generate a current delta signal line comprising the first and second signals resulting from the comparison of the current and the preceding scan lines; comparing the current and the preceding delta signal lines and inhibiting the generation of output signals when the current delta signal line contains only first signals and the preceding delta signal line also contains only first signals, generating as output signals a Mode A signal and the Y-address of the current scan line when the current delta signal line contains only first signals but the preceding delta signal line contains at least one second signal, and generating as output signals a Mode B signal followed by the Y-address of the current scan line when the current delta signal line contains at least one second signal; generating as output signals following each Mode B signal an X-address representing the positions of the first of each set of one or more immediately adjacent second signals in the current delta signal line followed by each of the second signals of the set if the number of second signals in the set is less than a predetermined number; and generating as output signals a first X-address representing the start of a set of immediately adjacent second signals whose number is greater than said predetermined number and a second X-address representing the end of the last recited set.
Claim 17
Dependent Claim 34 words
Method as in claim 12 wherein each of the scan lines is represented as a succession of binary bits, and wherein said first signals are binary zeros and said second signals are binary ones.
Claim 18
Dependent Claim 28 words
Method as in claim 12 wherein the scan line elemental areas which are compared are correspondingly positioned binary bits of the two video scan lines which are compared.
Claim 19
Dependent Claim 66 words
Method as in claim 12 including supplying defined binary coded signals representing the nonexistent preceding scan line when the current scan line is the first of a succession of scan lines and comparing the supplied signals with the first scan line, and supplying defined binary signals representing the nonexistent corresponding previous delta signal line and comparing the last recited supplied signals with the current delta line.
Claim 20
Dependent Claim 35 words
Method as in claim 15 wherein each of the video scan lines is represented by a succession of binary signals, and wherein said first signals are binary zeros and said second signals are binary ones.
Claim 21
Dependent Claim 27 words
Method as in claim 16 wherein said scan line element areas which are compared are correspondingly positioned binary bits of the two scan lines which are compared.

References Cited (Backward Citations)

US3061672A Cited
US3347981A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-04-01 1977-10-01 1978-04-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-04-01 1981-10-01 1982-04-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-04-01 1985-10-01 1986-04-02 $7700.00 Window Closed / Lapsed

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