US3801826A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input for shift registers
Assignee: AT&T Teletype Corp
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Filing: 1972-05-12
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Granted: 1974-04-02
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Expires: 1992-05-12
Abstract
Abstract A bucket-brigade (charge-transfer-type) shift register wherein an input capacitance is provided substantially equal to the interstage capacitance of the shift-register. The input capacitance is selectively grounded in response to input data signals of one type, after each charge transfer. Subsequently, the input capacitance is recharged to the optimum level for data charge transfer in order to maximize the number of stages possible before a refresh amplifier is needed.
Inventors
- 👤 S Gorski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:00
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/186
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
224 words
An Improved data shifting and storage circuit having a plurality of storage devices each having substantially the same storage capacity and serially interconnected by gating devices and coupled to first and second clock conductors, wherein the improvement comprises an input circuit comprising: a first gating device having a control electrode and a first controlled electrode and a second controlled electrode, the control electrode being connected to the first clock conductor and the second controlled electrode connected to one of said storage devices; a second gating device having a control electrode and a first controlled electrode and a second controlled electrode, the control electrode and the first controlled electrode being connected to the second clock conductor and the second controlled electrode being connected to the first controlled electrode of the first gating device; an input storage device having a capacity substantially equal to the capacity of said storage devices, the input storage device being connected between the second clock conductor and the second controlled electrode of the second gating device; and a third gating device having a control electrode and a first controlled electrode and a second controlled electrode, the first controlled electrode being connected to the first controlled electrode of the first gating device, the control electrode being connected to a first terminal and the second controlled electrode being connected to a second terminal.
Claim 2
Dependent Claim
224 words
An Improved data shifting and storage circuit having a plurality of storage devices each having substantially the same storage capacity and serially interconnected by gating devices and coupled to first and second clock conductors, wherein the improvement comprises an input circuit comprising: a first gating device having a control electrode and a first controlled electrode and a second controlled electrode, the control electrode being connected to the first clock conductor and the second controlled electrode connected to one of said storage devices; a second gating device having a control electrode and a first controlled electrode and a second controlled electrode, the control electrode and the first controlled electrode being connected to the second clock conductor and the second controlled electrode being connected to the first controlled electrode of the first gating device; an input storage device having a capacity substantially equal to the capacity of said storage devices, the input storage device being connected between the second clock conductor and the second controlled electrode of the second gating device; and a third gating device having a control electrode and a first controlled electrode and a second controlled electrode, the first controlled electrode being connected to the first controlled electrode of the first gating device, the control electrode being connected to a first terminal and the second controlled electrode being connected to a second terminal.
Claim 3
Dependent Claim
24 words
A combination according to claim 1 wherein the second terminal is connected to a conductor capable of assuming either of at least two voltages.
Claim 4
Dependent Claim
17 words
A combination according to claim 1 further comprising a data input terminal connected to the second terminal.
Claim 5
Dependent Claim
17 words
A combination according to claim 3 further comprising: a third clock conductor connected to the first terminal.
Claim 6
Dependent Claim
17 words
A combination according to claim 1 wherein the second terminal is connected to the first clock conductor.
Claim 7
Dependent Claim
17 words
A combination according to claim 5 further comprising a data input circuit connected to the first terminal.
Claim 8
Dependent Claim
22 words
A combination according to claim 1 further comprising an input terminal and wherein the second terminal is connected to the input terminal.
Claim 9
Dependent Claim
132 words
A data input circuit for a charge-transfer multivoltage type memory wherein the several stages of the memory include charge stores of equal magnitude, wherein a charge is transferred from stage to stage through the several stages, each charge store for storing at least two different states of data-representing charge voltage comprising: an input charge store of magnitude substantially no more than the magnitude of the charge stores of each of the several stages; means responsive to data signals for selectively discharging the charge of the input charge store to a voltage substantially beyond a range defined by the two states of data-representing charge voltage; and means operative after the selectively discharging means for recharging the input charge store to exactly the voltage of one of the two states of data-representing charge voltage.
Claim 10
Dependent Claim
132 words
A data input circuit for a charge-transfer multivoltage type memory wherein the several stages of the memory include charge stores of equal magnitude, wherein a charge is transferred from stage to stage through the several stages, each charge store for storing at least two different states of data-representing charge voltage comprising: an input charge store of magnitude substantially no more than the magnitude of the charge stores of each of the several stages; means responsive to data signals for selectively discharging the charge of the input charge store to a voltage substantially beyond a range defined by the two states of data-representing charge voltage; and means operative after the selectively discharging means for recharging the input charge store to exactly the voltage of one of the two states of data-representing charge voltage.
Claim 11
Dependent Claim
31 words
A circuit according to claim 8 wherein the recharging means comprises: a switching device for connecting the input charge store to a reference voltage after each operation of the discharging means.
Claim 12
Dependent Claim
27 words
A circuit according to claim 8 wherein the discharging means comprises a switching device for periodically connecting the input charge store to a selectively controlled discharge terminal.
Claim 13
Dependent Claim
16 words
A circuit according to claim 10 wherein the switching device is operated after each charge-transfer operation.
Claim 14
Dependent Claim
25 words
A circuit according to claim 8 wherein the discharging means comprises a switching device for selectively connecting the input charge store to a discharge terminal.
Claim 15
Dependent Claim
18 words
A circuit according to claim 12 comprising means for selectively operating the switching device after each charge-transfer operation.
Claim 16
Dependent Claim
38 words
A circuit according to claim 13 wherein the selectively operating Means comprises: means for generating a timing signal after each charge transfer operation; and means responsive to input data signals gating the timing signal to the switching device.
Claim 17
Independent Claim
109 words
A method of delivery of data to a charge-transfer-type shift register having charge storage elements in each stage which store binary data bits at either of two distinct voltage levels, gating devices for transferring charge sequentially from charge storage element to charge storage element, and a separate input charge storage element comprising: substantially matching the capacity of the input storage element to the storage elements of the several stages; discharging the input storage element of the input stage of the register to a voltage beyond a range defined by the two voltages; and recharging the charge voltage on the input storage element to one of said two voltage levels.
Claim 18
Independent Claim
109 words
A method of delivery of data to a charge-transfer-type shift register having charge storage elements in each stage which store binary data bits at either of two distinct voltage levels, gating devices for transferring charge sequentially from charge storage element to charge storage element, and a separate input charge storage element comprising: substantially matching the capacity of the input storage element to the storage elements of the several stages; discharging the input storage element of the input stage of the register to a voltage beyond a range defined by the two voltages; and recharging the charge voltage on the input storage element to one of said two voltage levels.
Claim 19
Independent Claim
90 words
A method of delivering data to a charge-transfer-type circuit wherein data are stored on charge storage devices having two data-representing voltage states and wherein charge is transferred from charge storage device to charge storage device by gating devices wherein the circuit has at least an input stage, comprising: selectively discharging the storage element of the input stage of the register to a voltage outside of a range defined by said two voltages; and correcting the charge on the storage element of the input stage to one of the two voltages.
Claim 20
Independent Claim
90 words
A method of delivering data to a charge-transfer-type circuit wherein data are stored on charge storage devices having two data-representing voltage states and wherein charge is transferred from charge storage device to charge storage device by gating devices wherein the circuit has at least an input stage, comprising: selectively discharging the storage element of the input stage of the register to a voltage outside of a range defined by said two voltages; and correcting the charge on the storage element of the input stage to one of the two voltages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-01 | 1977-10-01 | 1978-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-01 | 1981-10-01 | 1982-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-01 | 1985-10-01 | 1986-04-02 | $7700.00 | Window Closed / Lapsed |