← Back to Patent Explorer
US3803569A Expired / Lapsed US ⏱️ 0.0 years remaining

Failure check circuit

Assignee: Hitachi Ltd
•
Filing: 1972-03-27
•
Granted: 1974-04-09
•
Expires: 1992-03-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The failure state, due to disconnection or grounding of resistors connected in parallel, is checked in such a way that diodes are connected in series, respectively between the resistors and a common terminal for the parallel connection. A check signal is supplied to the other common terminal for the parallel connection, and the signals appearing at the connection points between the resistors and the diode are compared with the supplied check signal by using a logic circuit such as an AND gate.

Inventors

  • 👤 T Tanigami
  • 👤 T Iwasaki
  • 👤 S Watanabe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 19:37
CPC Classifications
B; B60; B60R; B60R21/00; B60R21/01; B60R21/017; B60R21/0173; B60R21/0176; G; G01; G01R; G01R31/00; G01R31/005; G01R31/006; G01R31/28; G01R31/2832; G01R31/2836

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 74 words
A failure check circuit comprising: a plurality of unit circuits each comprising a resistor and a diode connected in series; connection means for connecting said unit circuits in parallel between a first and a second common terminal; means for supplying a check signal to said first common terminal; and detecting means for detecting the existence of signals transmitted from said check signal supplying means to the connection points between said resistors and the diodes.
Claim 2
Dependent Claim 74 words
A failure check circuit comprising: a plurality of unit circuits each comprising a resistor and a diode connected in series; connection means for connecting said unit circuits in parallel between a first and a second common terminal; means for supplying a check signal to said first common terminal; and detecting means for detecting the existence of signals transmitted from said check signal supplying means to the connection points between said resistors and the diodes.
Claim 3
Dependent Claim 50 words
A failure check circuit according to claim 1, wherein said detecting means comprises a logic circuit and has a plurality of input terminals and an output terminal, said input terminals being respectively connected electrically to said connection points between said resistors and said diodes and to said first common terminal.
Claim 4
Dependent Claim 99 words
A failure check circuit comprising: a plurality of serial unit circuits each comprising a first diode, a resistor and a second diode which are connected in series; connection means for connecting said serial unit circuits in parallel between a first and a second common terminal, so as to directly connect said first and second diodes with said first and second common terminals, respectively; means for supplying a first check signal to said first common terminal; and means for detecting the signals transmitted from said check signal supplying means to the connection points between said resistors and said second diodes.
Claim 5
Dependent Claim 99 words
A failure check circuit comprising: a plurality of serial unit circuits each comprising a first diode, a resistor and a second diode which are connected in series; connection means for connecting said serial unit circuits in parallel between a first and a second common terminal, so as to directly connect said first and second diodes with said first and second common terminals, respectively; means for supplying a first check signal to said first common terminal; and means for detecting the signals transmitted from said check signal supplying means to the connection points between said resistors and said second diodes.
Claim 6
Dependent Claim 50 words
A failure check circuit according to claim 3, wherein said detecting means comprises a logic circit and has a plurality of input terminals and an output terminal, said input terminals being electrically connected to said connection points between said resistors and said second diodes and to said first common terminal.
Claim 7
Dependent Claim 52 words
A failure check circuit according to claim 4, comprising a second means for supplying second check signals to the connection points between said first diodes and said resistors and a second detecting means for detecting the signal transmitted from said second means for supplying second check signals to said second common terminal.
Claim 8
Dependent Claim 42 words
A failure check circuit according to claim 5, wherein said second detecting means comprises a logic circuit and has a plurality of input terminals respectively connected to said common terminal and to said connection points between said first diodes and said resostors.
Claim 9
Dependent Claim 24 words
A failure check circuit according to claim 6, wherein said second check signals comprise pulse signals shifted in time with respect to each other.
Claim 10
Dependent Claim 23 words
A failure check circuit according to claim 3, wherein said first check signal supplying means comprises means for generating a series of pulses.
Claim 11
Dependent Claim 58 words
A failure check circuit according to claim 5, wherein said means for supplying second check signals comprises a plurality of frequency dividers, the inputs of which are connected in common to the output of said first check signal supplying means and the respective outputs of which are connected to respective connection points between said first diodes and resistors.
Claim 12
Dependent Claim 20 words
A failure check circuit according to claim 9, wherein each of said frequency dividers has a different frequency division characteristic.
Claim 13
Dependent Claim 32 words
A failure check circuit according to claim 3, wherein each of said first anD second diodes is connected to pass current in the same direction between said first and second common terminals.
Claim 14
Dependent Claim 26 words
A failure check circuit according to claim 1, wherein said check signal is supplied to said first common terminal for checking the condition of said resistors.
Claim 15
Dependent Claim 26 words
A failure check circuit according to claim 3, wherein said check signal is supplied to said first common terminal for checking the condition of said resistors.
Claim 16
Dependent Claim 40 words
A failure check circuit according to claim 3, wherein said plurality of serial unit circuits serve for activating an occupant safety device of a vehicle, and said resistors of said unit circuits are firing resistors for activating the safety device.
Claim 17
Dependent Claim 42 words
A failure check circuit according to claim 5, wherein said plurality of unit circuits serve for activating an occupant protective safety device of a vehicle, and said resistors of said unit circuits are firing resistors for activating the occupant protective safety device.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-04-08 1977-10-08 1978-04-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-04-08 1981-10-08 1982-04-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-04-08 1985-10-08 1986-04-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag