Digital acceleration measurement device

Claim 2

Negative feedback pulse rate responsive means for determining the rate of change of a detected pulse rate comprising in combination a clocked accumulating register having a clock input adapted to be responsive to an applied variable-rate pulse input, comparator means having a first input responsive to a preselected parametric interval represented by the periodicity of said detected pulse rate and also having a second input responsively coupled to an output of said accumulating register, and further having an output drivingly coupled to an input of said register, said output of said comparator means providing a signal indicative of the time-rate of change of the pulse rate of said applied pulse rate.

Claim 3

The device of claim 1 in which there is further provided compensatorily clocked means for preserving the digital resolution of said acceleration indicative output signal over a wide range of pulse rate input conditions, in which a clock input of said accumulating register is responsive to said detected pulse rate and in which a counting input of said accumulating register is input coupled to the output of said comparator.

Claim 4

The device of claim 2 in which said comparator has a third input responsive to a bias source indicative of an analog resolution limit associated with the pulses of said detected pulse rate, a clocked second register interposed between an output of said first register and the associated input to said comparator, said clocked second register being clocked at a preselected clock rate and cleared at said detected pulse rate.

Claim 5

The device of claim 3 in which there is further provided a third clocked register interposed at the acceleration signalling output of said comparator and clocked at said detected pulse rate and cleared at a preselected rate substantially less than said preselected clock rate of said second register.

Claim 6

The device of claim 2 in which said compensatorily clocked means comprises a clocked second register interposed between said output of said accumulating register and said second input of said comparator, said second register being input coupled to said accumulating register; and a clocked third register input coupled to said output of said comparator, said third register being clocked and said second register being reset commonly at said detected pulse rate, said second register being clocked and said third register being reset at mutually exclusive preselected clock rates.

Claim 7

The device of claim 2 in which said compensatorily clocked means comprises a clocked second register interposed between said output of said accumulating register and said second input of said comparator, said second register being input coupled to said accumulating register; and a clocked third register input coupled to said output of said comparator said second register being clocked at a preselected rate and being reset at said detected pulse rate, said third register being clocked at said detected pulse rate and being reset at a second preselected clock rate substantially less than the first preselected clocked rate of said second register.

Claim 8

Pulse rate responsive means for determining the rate of change of a detected pulse rate comprising in combination a clocked first register 24 having a clock input adapted to be responsive to said detected pulse rate; a clocked second register 25 having a clock input responsive to a first preselected periodic clock source and further having a clearance input adapted to be responsive to said detected pulse rate and a counting input responsive to an output of said first register; a bias signal source Do representing a detector resolution limit in the detection of said detected pulse rate; a clocked comparator 20 responsive to the output of said source and sAid clocked second register for providing a signal indicative of the difference therebetween, a clocking input of said comparator adapted to be responsive to said detected pulse rate; a clocked third register 26 having a clock input adapted to be responsive to said detected pulse rate, said clocked first and third registers 24 and 26 being commonly responsive to said difference signal response of said comparator, said clocked third register 26 being cleared in response to a second preselected periodic clock source having a clock rate substantially less than said first clock source and providing an output indicative of said rate of change of said detected pulse rate.

Claim 9

Pulse rate responsive means for determining the rate of change of a detected pulse rate comprising in combination a clocked first register 24 having a clock input adapted to be responsive to said detected pulse rate; a clocked second register 25 having a clock input responsive to a first preselected periodic clock source and further having a clearance input adapted to be responsive to said detected pulse rate and a counting input responsive to an output of said first register; a bias signal source Do representing a detector resolution limit in the detection of said detected pulse rate; a clocked comparator 20 responsive to the output of said source and sAid clocked second register for providing a signal indicative of the difference therebetween, a clocking input of said comparator adapted to be responsive to said detected pulse rate; a clocked third register 26 having a clock input adapted to be responsive to said detected pulse rate, said clocked first and third registers 24 and 26 being commonly responsive to said difference signal response of said comparator, said clocked third register 26 being cleared in response to a second preselected periodic clock source having a clock rate substantially less than said first clock source and providing an output indicative of said rate of change of said detected pulse rate.

Claim 10

Pulse rate responsive means for determining the rate of change of a detected pulse rate comprising in combination a first, second and third clocked register said first and third registers being commonly adapted to be clocked by said detected pulse rate, and said second register being clocked at a first preselected clock rate, said second register being adapted to be cleared at said detected pulse rate and said third register being cleared at a second preselected clock rate substantially less than said first preselected clock rate, said second register being input-coupled to an output of said first register; and a clocked comparator having a first input coupled to a bias source indicative of an analog resolution limit associated with the pulses of such detected pulse rate, and further having both a second input coupled to an output of said second clocked register and a clock input adapted to be responsive to said detected pulse rate, said first and third registers being commonly input-coupled to an output of said comparator; the output of said third register being indicative of said rate of change of said detected pulse rate.

Claim 11

Pulse rate responsive means for determining the rate of change of a detected pulse rate comprising in combination a first, second and third clocked register said first and third registers being commonly adapted to be clocked by said detected pulse rate, and said second register being clocked at a first preselected clock rate, said second register being adapted to be cleared at said detected pulse rate and said third register being cleared at a second preselected clock rate substantially less than said first preselected clock rate, said second register being input-coupled to an output of said first register; and a clocked comparator having a first input coupled to a bias source indicative of an analog resolution limit associated with the pulses of such detected pulse rate, and further having both a second input coupled to an output of said second clocked register and a clock input adapted to be responsive to said detected pulse rate, said first and third registers being commonly input-coupled to an output of said comparator; the output of said third register being indicative of said rate of change of said detected pulse rate.

Claim 12

In an anti-skid brake control system for wheeled vehicles and responsive to braked wheel velocity and acceleration and having means for providing a detected pulse train indicative of wheel rotation, pulse rate responsive means for determining the rate of change of a detected pulse rate of said pulse train comprising in combination a first, second and third clocked register said first and third registers being commonly adapted to be clocked by said detected pulse rate, and said third register being clocked at a first preselected clock rate, said second register being adapted to be cleared at said detected pulse rate and said third register being cleared at a second preselected clock rate substantially greater than said first preselected clock rate, said second register being input-coupled to an output of said first register; and a clocked comparator having a first input coupled to a bias source indicative of an analog resolution limit associated with the pulses of such detected pulse rate, and further having both a second input coupled to an output of said second clocked register and a clock input adapted to be responsive to said detected pulse rate, said first and third registers being commonly input-coupled to an output of said comparator; the output of said third register being indicative of said rate of change of said detected pulse rate.

Claim 13

In an anti-skid brake control system for wheeled vehicles and responsive to braked wheel velocity and acceleration and having means for providing a detected pulse train indicative of wheel rotation, pulse rate responsive means for determining the rate of change of a detected pulse rate of said pulse train comprising in combination a first, second and third clocked register said first and third registers being commonly adapted to be clocked by said detected pulse rate, and said third register being clocked at a first preselected clock rate, said second register being adapted to be cleared at said detected pulse rate and said third register being cleared at a second preselected clock rate substantially greater than said first preselected clock rate, said second register being input-coupled to an output of said first register; and a clocked comparator having a first input coupled to a bias source indicative of an analog resolution limit associated with the pulses of such detected pulse rate, and further having both a second input coupled to an output of said second clocked register and a clock input adapted to be responsive to said detected pulse rate, said first and third registers being commonly input-coupled to an output of said comparator; the output of said third register being indicative of said rate of change of said detected pulse rate.