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US3818203A Expired / Lapsed US ⏱️ 0.0 years remaining

Matrix shifter

Assignee: Honeywell Inc
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Filing: 1973-08-27
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Granted: 1974-06-18
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Expires: 1993-08-27
📄 Original PDF 🌐 Google Patents

Abstract

Abstract The disclosure describes a matrix shifter comprising right and left shift conductors which operate switches controlling the flow of information from input conductors to output conductors. The switches are arranged in the form of a matrix so that logical, arithmetic and rotational multibit shifting can be achieved with a single pass by energizing at most two control shift conductors at a time.

Inventors

  • 👤 A Perlowski
  • 👤 R Wallace
  • 👤 R Magers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 06:44
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/015

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 462 words
In a system for handling digital data in the form of N information bits represented by discrete logic states including a plurality of N input conductors representing bit positions 0 through N minus 1, where N is a positive integer, improved apparatus for shifting the data with respect to the bit positions comprising: N output conductors representing bit positions 0 through N minus 1; a zero shift conductor for transmitting a zero shift signal; zero shift switch means operatively connecting each input conductor to a corresponding output conductor representing a like bit position for switching each output conductor to the same logic state as the corresponding input conductor in response to the zero shift signal; right shift conductors representing right bit position shifts; right shift switch sets representing right bit position shifts, each switch set being operated by one of said right shift conductors representing a like right bit position shift; right shift switch means in each right shift switch set for operatively connecting one of said input conductors to one of said output conductors representing a bit position exceeding the bit position of said one input conductor by the number of right bit position shifts represented by the right shift conductor operating the switch means; left shift conductors representing left bit position shifts; left shift switch sets representing left bit position shifts, each switch set being operated by one of said left shift conductors representing a like left bit position shift; left shift means in each left shift switch set for operatively connecting one of said input conductors to one of said output conductors representing a bit position less than the bit position of the one input conductor by the number of left bit position shifts represented by the left shift conductor operating the left shift switch means; first control means for shifting the data present on the input conductors to the right by energizing the right shift conductor representing the number of right bit positions to be shifted; second control means for shifting the data Present on the input conductors to the left by energizing the left shift conductor representing the number of left bit positions to be shifted; third control means for rotating the data present on the input conductors to the right by energizing the right shift conductor representing the number of right bit positions to be rotated and by energizing the left shift conductor representing N minus the number of right bit positions to be rotated; and fourth control means for rotating the data present on the input conductors to the left by energizing the left shift conductor representing the number of left bit positions to be rotated and by energizing the right shift conductor representing N minus the number of left bit positions to be rotated.
Claim 2
Dependent Claim 462 words
In a system for handling digital data in the form of N information bits represented by discrete logic states including a plurality of N input conductors representing bit positions 0 through N minus 1, where N is a positive integer, improved apparatus for shifting the data with respect to the bit positions comprising: N output conductors representing bit positions 0 through N minus 1; a zero shift conductor for transmitting a zero shift signal; zero shift switch means operatively connecting each input conductor to a corresponding output conductor representing a like bit position for switching each output conductor to the same logic state as the corresponding input conductor in response to the zero shift signal; right shift conductors representing right bit position shifts; right shift switch sets representing right bit position shifts, each switch set being operated by one of said right shift conductors representing a like right bit position shift; right shift switch means in each right shift switch set for operatively connecting one of said input conductors to one of said output conductors representing a bit position exceeding the bit position of said one input conductor by the number of right bit position shifts represented by the right shift conductor operating the switch means; left shift conductors representing left bit position shifts; left shift switch sets representing left bit position shifts, each switch set being operated by one of said left shift conductors representing a like left bit position shift; left shift means in each left shift switch set for operatively connecting one of said input conductors to one of said output conductors representing a bit position less than the bit position of the one input conductor by the number of left bit position shifts represented by the left shift conductor operating the left shift switch means; first control means for shifting the data present on the input conductors to the right by energizing the right shift conductor representing the number of right bit positions to be shifted; second control means for shifting the data Present on the input conductors to the left by energizing the left shift conductor representing the number of left bit positions to be shifted; third control means for rotating the data present on the input conductors to the right by energizing the right shift conductor representing the number of right bit positions to be rotated and by energizing the left shift conductor representing N minus the number of right bit positions to be rotated; and fourth control means for rotating the data present on the input conductors to the left by energizing the left shift conductor representing the number of left bit positions to be rotated and by energizing the right shift conductor representing N minus the number of left bit positions to be rotated.
Claim 3
Dependent Claim 15 words
Apparatus, as claimed in claim 1, wherein each switch means comprises a semi-conductor switching device.
Claim 4
Dependent Claim 42 words
Apparatus, as claimed in claim 1, wherein each switch means comprises a transistor having a base element operatively connected to an input conductor, a collector element operatively connected to an output conductor and an emitter element operatively connected to a shift conductor.
Claim 5
Dependent Claim 32 words
Apparatus, as claimed in claim 1, wherein the number of right shift conductors equals N minus 1 and wherein the right shift conductors represent right bit position shifts 1 through N minus
Claim 6
Dependent Claim 32 words
Apparatus, as claimed in claim 4, wherein the number of left shift conductors equals N minus 1 and wherein the left shift conductors represent left bit position shifts 1 through N minus
Claim 7
Dependent Claim 34 words
Apparatus, as claimed in claim 5, wherein the number of right shift switch sets equals N minus 1 and wherein the right shift switch sets represent right bit position shifts 1 through N minus
Claim 8
Dependent Claim 34 words
Apparatus, as claimed in claim 6, wherein the number of left shift switch sets equals N minus 1 and wherein the left shift switch sets represent left bit position shifts 1 through N minus
Claim 9
Dependent Claim 32 words
Apparatus, as claimed in claim 1, wherein the number of right shift switch means in each right shift switch set equals N minus the right bit position shifts represented by said set.
Claim 10
Dependent Claim 32 words
Apparatus, as claimed in claim 8, wherein the number of left shift switch means in each left shift switch set equals N minus the left bit position shifts represented by said set.
Claim 11
Dependent Claim 163 words
Apparatus, as claimed in claim 1, and further comprising: arithmetic right shift conductors representing arithmetic right bit position shifts 1 through N minus 1; N minus 1 sets of arithmetic right switches representing arithmetic right bit position shifts 1 through N minus 1, each set operatively connecting a corresponding arithmetic right shift conductor representing a like number of bit position shifts to each of the output conductors representing a bit position equal to or less than the said like number of bit position shifts minus 1; and fifth control means for energizing the arithmetic right shift conductor representing bit position shifts equal to the number of positions to be shifted right at the same time the first control means energizes the right shift conductor representing the number of right bit positions to be shifted, so that the output conductors are operatively connected to the energized arithmetic right shift conductor by the switches, whereby the output conductors are switched to a predetermined logic state.

References Cited (Backward Citations)

US3588483A Cited
US3731073A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-06-17 1977-12-17 1978-06-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-06-17 1981-12-17 1982-06-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-06-17 1985-12-17 1986-06-18 $7700.00 Window Closed / Lapsed

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