US3828230A
Expired / Lapsed
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Field effect semiconductor device having an unsaturated triode vacuum tube characteristi
Assignee: ZAIDAN HOJIN HONDOTAI KENKYN S
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Filing: 1972-07-28
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Granted: 1974-08-06
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Expires: 1992-07-28
Abstract
Abstract A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain volage is above the threshold voltage exhibiting a linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.
Inventors
- 👤 J Nishizawa
- 👤 T Terasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:18
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3241; H03F1/3264; H03F1/327; H10; H10D; H10D30/00; H10D30/202; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/145
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
297 words
A field effect semiconductor device capable of exhibiting unsaturable drain voltage versus drain current characteristics comprising: a first and second spaced gate region formed of a relatively high impurity doped semiconductor material and having a first conductivity type; a semiconductor region located adjacent to said first and second spaced regions and having an opposite conductivity type, said second region being formed of a substantially intrinsic semiconductor material of a low carrier concentration, said semiconductor region having a portion forming a current channel between said first and second gate regions, said channel including the semiconductor region disposed between respective junctions formed with said first and second gate regions defining the sides of said channels and including a depletion layer incident to each of said junctions, said depletion layers being contiguous or overlapping each other to achieve a pinchoff condition within said channel in the absence of a reverse bias voltage applied to said first and second gate regions; a source region located along said channel for supplying a current thereto; a drain region spaced from said source region along said channel for providing an output current, said source region and drain region comprising semiconductor regions having the same conductivity type as said channel region; gate biasing means for applying a reverse bias voltage to said first and second gate regions to increase the effective length of the overlapping depletion layers along said current channel with an increase in magnitude of the applied reverse bias voltage to thereby determine a threshold drain voltage, wherein the application of a drain voltage greater than said threshold voltage allows the carriers from the source region to travel toward said drain region in the depletion layer existing along the current channel in the same manner as that exhibited by a triode vacuum tube.
Claim 2
Dependent Claim
297 words
A field effect semiconductor device capable of exhibiting unsaturable drain voltage versus drain current characteristics comprising: a first and second spaced gate region formed of a relatively high impurity doped semiconductor material and having a first conductivity type; a semiconductor region located adjacent to said first and second spaced regions and having an opposite conductivity type, said second region being formed of a substantially intrinsic semiconductor material of a low carrier concentration, said semiconductor region having a portion forming a current channel between said first and second gate regions, said channel including the semiconductor region disposed between respective junctions formed with said first and second gate regions defining the sides of said channels and including a depletion layer incident to each of said junctions, said depletion layers being contiguous or overlapping each other to achieve a pinchoff condition within said channel in the absence of a reverse bias voltage applied to said first and second gate regions; a source region located along said channel for supplying a current thereto; a drain region spaced from said source region along said channel for providing an output current, said source region and drain region comprising semiconductor regions having the same conductivity type as said channel region; gate biasing means for applying a reverse bias voltage to said first and second gate regions to increase the effective length of the overlapping depletion layers along said current channel with an increase in magnitude of the applied reverse bias voltage to thereby determine a threshold drain voltage, wherein the application of a drain voltage greater than said threshold voltage allows the carriers from the source region to travel toward said drain region in the depletion layer existing along the current channel in the same manner as that exhibited by a triode vacuum tube.
Claim 3
Dependent Claim
47 words
The field effect semiconductor device of claim 1, in which the extent of the depth of said depletion layers is determined by the contact potential at said junction and by the impurity concentration of the semiconductor material of the channel region, wherein the gate-to-gate distance is determined.
Claim 4
Dependent Claim
44 words
The field effect semiconductor device of claim 1, in which the output current at said drain region exhibits an unsaturated non-linear characteristic with respect to the applied drain voltage when said drain voltage is above a threshold determined by a given gate bias voltage.
Claim 5
Dependent Claim
61 words
The field effect semiconductor device of claim 1, in which said channel constituting the semiconductor region is formed of a plate elongated in the source-to-drain direction, and said first and second gate regions are formed on the two principal surfaces of said plate sandwiching therebetween said current channel, the dEpletion layers extending from said gates and contacting or overlapping each other.
Claim 6
Dependent Claim
36 words
The field effect semiconductor device of claim 4, in which each of said gate electrodes has a dimension in the longitudinal direction along said current channel small enough to reduce the series resistance of the channel.
Claim 7
Dependent Claim
32 words
The field effect semiconductor device of claim 1, in which said source and drain regions and said gate regions are disposed on one surface of the semiconductor material constituting the current channel.
Claim 8
Dependent Claim
26 words
The field effect semiconductor device of claim 1, in which said channel constituting semiconductor material is silicon having an impurity concentration below the order of 1015/cm3.
Claim 9
Dependent Claim
45 words
The field effect semiconductor device of claim 4, in which said current channel between the gate regions has a diametrical dimension of at most three times the total width of the total depletion layers calculated from the assumption of perfect ionization in the depletion layers.
Claim 10
Dependent Claim
38 words
A field effect transistor accoridng to claim 1, wherein said semiconductor substrate is cylindrical and the gate electrode has a hollow cylindrical shape formed on the side surface of said cylindrical substrate surrounding the current channel extending therewithin.
Claim 11
Dependent Claim
19 words
A field effect transistor according to claim 1, wherein said gate electrode is annular and surrounds the source electrode.
Claim 12
Dependent Claim
31 words
A field effect transistor according to claim 1, wherein said semiconductor substrate is cylindrical and said gate electrode is formed on an intermediate portion of the side surface of said cylinder.
Claim 13
Dependent Claim
23 words
A field effect transistor according to claim 1, wherein a plurality of said gate regions are formed in and traversing the current channel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |