High-voltage integrated driver circuit and memory embodying same

Claim 2

A high voltage integrated driver circuit comprising: a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse, said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source so as to maintain said third conductive electrode at said fixed potential, means connecting said fourth conductive electrode to said firstrecited control electrode so as to maintain said fourth conductive electrode and said first-recited control electrode at the same potential, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive.

Claim 3

A high-voltage integrated driver circuit is recited in claim 1 wherein said first-recited transistor and said second transistor are field-effect transistors, said first and third conductive electrodes are source electrodes, said second and fourth conductive electrodes are drain electrodes, and said control electrodes are gate electrodes.

Claim 4

A high-voltage integrated driver circuit as recited in claim 1 and comprising means for applying a restore pulse to charge said control electrode to an initial voltage level before activation of said signal pulse applying means.

Claim 5

A high-voltage integrated driver circuit as recited in claim 1 and comprising positive feedback means connecting said first conductive electrode to said control electrode.

Claim 6

A high-voltage integrated driver circuit as recited in claim 4 wherein said positive feedback means comprises a capacitor.

Claim 7

A high voltage integrated driver circuit comprising: a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse, said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive comprising a logic gate having a plurality of inputs adapted to receive binary signals.

Claim 8

A high voltage integrated driver circuit comprising: a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse, said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive comprising a logic gate having a plurality of inputs adapted to receive binary signals.

Claim 9

A high-voltage integrated driver circuit as recited in claim 6 wherein said first-recited transistor and said second transistor are field-effect transistors, said first and third conductive electrodes are source electrodes, said second and fourth conductive electrodes are drain electrodes, and said control electrodes are gate electrodes.

Claim 10

A high-voltage integrated driver circuit as recited in claim 2 and comprising means for applying a restore pulse to charge said first control electrode to an initial voltage level before activation of said signal pulse applying means.

Claim 11

A high-voltage integrated driver circuit as recited in claim 8 and comprising positive feedback means connecting said first conductive electrode to said first control electrode.

Claim 12

A high-voltage integrated driver circuit as recited in claim 9 wherein said positive feedback means comprises a capacitor.

Claim 13

A high-voltage integrated driver circuit as recited in claim 10, wherein said logic gate comprises a transistor having a plurality of electrodes, each of said inputs being connected to a respective one of said logic gate transistor electrodes.

Claim 14

A high-voltage integrated driver circuit as recited in claim 11, wherein said logic gate transistor is a bipolar transistor, each of said plurality of electrodes being an emitter electrode.

Claim 15

A high-voltage integrated driver circuit as recited in claim 12 wherein said selectably operable means comprises a third transistor having a fifth conductive electrode, a sixth conductive electrode, and a third control electrode, means connecting said fifth conductive electrode to a fixed potential source, means connecting said sixth conductive electrode to said output, and means connecting said third control electrode to said means for selectably applying a signal so as to render said third transistor either conductive or nonconductive.

Claim 16

A memory system for digital computers and other digital equipment and comprising an array of memory cells arranged in a plurality of rows, each memory cell including a floating-gate avalanche-injection transistor, a plurality of word-lines each connected to a respective row of said memory cells, each of said word-lines having associated therewtih a respective driver circuit as recited in claim 6, each of said driver circuit outputs being drivingly connected to the respective word-line.

Claim 17

A memory system for digital computers and other digital equipment and comprising an array of memory cells arranged in a plurality of rows, each memory cell including a floating-gate avalanche-injection transistor, a plurality of word-lines each connected to a respective rOw of said memory cells, each of said word-lines having associated therewtih a respective driver circuit as recited in claim 13, each of said driver circuit outputs being drivingly connected to the respective word-line, said array of memory cells and said driver circuits associated therewith being embodied in a single monolithic integrated circuit chip.

Claim 18

A high voltage integrated driver circuit comprising: a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse, said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive, a third transistor having a fifth conductive electrode, a sixth conductive electrode, and a third control electrode, means connecting said fifth conductive electrode to a fixed potential source, means connecting said sixth conductive electrode to said output, and means connecting said third control electrode to said means for selectably applying a signal so as to render said third transistor either conductive or non-conductive.

Claim 19

A high voltage integrated driver circuit comprising: a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse, said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive, a third transistor having a fifth conductive electrode, a sixth conductive electrode, and a third control electrode, means connecting said fifth conductive electrode to a fixed potential source, means connecting said sixth conductive electrode to said output, and means connecting said third control electrode to said means for selectably applying a signal so as to render said third transistor either conductive or non-conductive.

Claim 20

A high-voltage integrated driver circuit as recited in claim 16 wherein said first-recited transistor, said second transistor and said third transistor are field-effect transistors, said first, third and fifth conductive electrodes are source electrodes, said second, fourth and sixth conductive electrodes are drain electrodes, and said control electrodes are gate electrodes.

Claim 21

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in the plurality of rows, each memory cell including a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; each of said driver circuit outputs being drivingly connected to the respective word line.

Claim 22

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in the plurality of rows, each memory cell including a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; each of said driver circuit outputs being drivingly connected to the respective word line.

Claim 23

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in a plurality of rows, each memory cell includinG a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive; and means for applying a restore pulse to charge said control electrode to an intial voltage level before activation of said signal pulse applying means, each of said driver circuit outputs being drivingly connected to the respective word line, said array of memory cells in said driver circuits associated therewith being embodied in a single monolithic integrated circuit chip.

Claim 24

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in a plurality of rows, each memory cell includinG a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby to maintain said first conductive electrode and said output at a first predetermined voltage level, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive; and means for applying a restore pulse to charge said control electrode to an intial voltage level before activation of said signal pulse applying means, each of said driver circuit outputs being drivingly connected to the respective word line, said array of memory cells in said driver circuits associated therewith being embodied in a single monolithic integrated circuit chip.

Claim 25

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in a plurality of rows, each memory cell including a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a high voltage integrated driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby maintain said first conductive electrode and said output at a first predetermined voltage, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive; said first-recited transistor and said second transistor being field effect transistors, said first and third conductive electrodes being source electrodes, said second and fourth conductive electrodes being drain electrodes, and said control electrodes being gate electrodes, each of said driver circuit outputs beIng drivingly connected to the respective word line.

Claim 26

A memory system for digital computers and other digital equipment and comprising: an array of memory cells arranged in a plurality of rows, each memory cell including a floating gate avalanche injection transistor, a plurality of word lines each connected to a respective row of said memory cells, each of said word lines having associated therewith a respective driver circuit; said driver circuit comprising a high voltage integrated driver circuit comprising a transistor having a first conductive electrode, a second conductive electrode, and a control electrode, an output connected to said first conductive electrode, means for applying a signal pulse of a predetermined polarity to said second conductive electrode, and selectably operable means conditioned either to a first state for clamping the voltage of said control electrode to cut off said transistor and thereby maintain said first conductive electrode and said output at a first predetermined voltage, or to a second state for unclamping the voltage of said control electrode to permit the voltage of said first conductive electrode to swing in the direction of said predetermined polarity in response to said signal pulse; said selectably operable means comprising a second transistor having a third conductive electrode, a fourth conductive electrode, and a second control electrode, a fixed potential source, means connecting said third conductive electrode to said fixed potential source, means connecting said fourth conductive electrode to said first-recited control electrode, and means for selectably applying a signal to said second control electrode to render said second transistor either conductive or non-conductive; said first-recited transistor and said second transistor being field effect transistors, said first and third conductive electrodes being source electrodes, said second and fourth conductive electrodes being drain electrodes, and said control electrodes being gate electrodes, each of said driver circuit outputs beIng drivingly connected to the respective word line.