Tone generating system

Claim 3

The system of claim 1 wherein said extractor includes: a level crossing detector for producing an output when said level of said waveform passes through a first reference level; a threshold detector for producing an output when ssaid level of said waveform exceeds a second reference level; and a flip-flop having a first side connected to said level crossing detector and a second side connected to said threshold detector, said second side having an output terminal, whereby said square wave is produced at said output terminal of said flip-flop.

Claim 4

The system of claim 1 wherein said second means includes: a first register adapted for accumulating a pulse count therein; and a frequency source responsive to said first means for producing pulses to said first register for a period of time related to said fundamental frequency of said input signal whereby said count accumulated in said register is a measure of said frequency.

Claim 5

The system of claim 3 wherein said second means further includes: a generator responsive to said first means for producing first and second control pulses at a rate determined by said fundamental frequency, said first control pulse having a duration proportional to the period of said input signal; means for connecting said second control pulse to said first register for initializing said count therein; and gating means responsive to said first control signal for gating said pulses to said first register for said duration.

Claim 6

The system of claim 4 wherein said input signal comprises a plurality of discrete segments separated by time intervals, said first means determines said fundamental frequency of each of said segments, and said second means further includes; a detector responsive to said first means for detecting said fundamental frequency of each of said segments and generating a trigger output in response thereto; and means for connecting said trigger output to said generator for causing said generator to produce one of each of said first and second control pulses for each of said segments, whereby said count accumulated in said first register at a particular time is related to said fundamental frequency of one of said segments comprising said input at said particular time.

Claim 7

The system of claim 4 wherein said input signal comprises a continuous frequency-varying wave, said first means determines said fundamental frequency for each cycle of said wave, and said second means includes: a divider responsive to said first means for generating a trigger output for every nth cycle of said wave; and means for connecting said trigger output to said generator for causing said generator to produce one of each of said First and second control pulses at ever nth one of said cycles, said duration of said first control pulse being proportional to the period of said nth cycle, so that said count accumulated in said first register is updated every nth cycle and thereby tracks the frequency of said wave, where n is any positive integer.

Claim 8

The system of claim 6 wherein n equals four.

Claim 9

The system of claim 3 wherein said output means includes: a second register having an initial count therein; means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence; means for cycling said second register at a rate proportional to the frequency of said frequency source to cause returns of said second register to said initial count; and means for detecting said returns to said initial count and producing an output signal in response thereto whereby said output signal is repeatedly produced and has a frequency related to said fundamental frequency of said input signal.

Claim 10

The system of claim 8 wherein said initial count equals zero, said accumulated count is added to said second register and said cycling means causes said second register to count down from said accumulated count to zero.

Claim 11

The system of claim 8 wherein said changing means includes: a third register for receiving and storing said accumulated count from said first register; a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns to said initial count; and a second gate responsive to said detecting means for transferring said accumulated count from said first register to said third register whenever a new one of said counts is accumulated in said first register whereby said third register always contains a count related to said fundamental frequency of said input signal.

Claim 12

The system of claim 8 including: a divider between said frequency source and said first register for dividing the frequency of said pulses from said frequency source by a factor of m, where m is any positive integer; and said cycling means includes means for connecting said frequency source to said second register for causing said second register to cycle at a rate m times the rate at which said first register accumulates said count whereby said output signal has a frequency m times said frequency of said input signal.

Claim 13

The system of claim 11 wherein m equals 8.

Claim 14

The system of claim 8 further including division circuits for dividing said frequency of said output signal by a plurality of preselected numbers so that a plurality of outputs having frequencies related to said fundamental frequency of said input signal by any desired ratio can be obtained.

Claim 15

The system of claim 13 further including pulse shaping circuits for shaping said plurality of outputs and means for amplifying said outputs whereby a variety of voicings having frequencies related to said frequency of said input signal can be obtained.

Claim 16

The system of claim 3 including: a plurality of decoders each of which is responsive to the accumulation of a respective allowable count in said first register; and means responsive to said decoders in the absence of one of said respective counts for extending said period of time during which said pulses are provided to said first register until one of said respective allowable counts is accumulated in said first register, whereby said accumulated count is restricted to one of said respective allowable counts.

Claim 17

The system of claim 15 including a subtractor between said frequency source and said first register for subtracting the first x of said pulses provided to said first register, where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said Respective counts.

Claim 18

The system of claim 16 wherein x approximately equals one-half the average difference between said respective allowable counts whereby said count accumulated in said first register is normally rounded off to the nearer one of said two closest ones of said respective counts.

Claim 19

The system of claim 16 wherein x equals 4.

Claim 20

The system of claim 1 including buffer and amplifier circuits for isolating and amplifying said input signal, respectively, applied to said first means.

Claim 21

The system of claim 19 wherein said buffer circuit provides a gain of approximately one and said amplifying circuit provides a gain of approximately 50.

Claim 22

The system of claim 1 wherein said output means comprises; a counting means having an initial count therein; means for changing said initial count by an amount proportional to said signal stored in said second means in a repetitive sequence; means for repeatedly cycling said counting means at a preselected rate to cause returns thereof to said initial count; and means for detecting said returns to said initial count and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency of said input signal.

Claim 23

The system of claim 21 wherein said changing means includes: a storing means responsive to said signal in said second means for accumulating a count therein proportional to said signal; first gating means responsive to said detecting means for transferring said count in said storing means to said counting means each time said counting means returns to said initial count; and means responsive to the storing of a new one of said signals in said second means for updating said count accumulated in said storing means.

Claim 24

The system of claim 22 further including division circuits for dividing said frequencies of said outputs by a plurality of preselected numbers so that a plurality of outputs having frequencies related to said fundamental frequency of said input signal by any desired ratios can be obtained.

Claim 25

The system of claim 23 further including pulse shaping circuits for shaping said plurality of outputs and amplifying means for amplifying said plurality of outputs whereby a variety of voicings having frequencies related to said fundamental frequency of said input signal can be obtained.

Claim 26

The system of claim 1 wherein said second means includes a first register for accumulating a pulse count therein, and a frequency source responsive to said frequency extractor for providing pulses to said first register for a period of time proportional to said fundamental frequency so that said count accumulated by said first register is proportional to said fundamental frequency; and said output means includes a second register having an initial count therein, means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence, means for repetitively cycling said second register at a rate proportional to the frequency of said frequency source to cause returns thereof to said initial count, means for detecting said returns and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency and being produced in a repetitive sequence.

Claim 27

The system of claim 25 wherein said second means further includes a generator responsive to said extractor for generating first and second control pulses, said second control pulse being utilized to initialize said first register, said first control pulse having a duration equal to said fundamental frequency, and a gate responsive to said first control pulse to transfer said pulses to said first register.

Claim 28

The system of claim 26 including a divider for dividing the frequency of said pulses transferred to said first register by a factor of m and wherein said cycling means includes means connecting said pulses to said second regiSter to cause said second register to count at a rate m times said first register, whereby said detecting means produces an output signal having a frequency m times said fundamental frequency where m is any positive integer.

Claim 29

The system of claim 27 wherein said changing means includes a third register for receiving and storing said accumulated count, a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns of said second register to said initial count; and a second gate responsive to said detecting means and said generator means for transferring said accumulated count from said first register to said third register after the termination of each of said control pulses and during a time when said first gate is inactive.

Claim 30

The system of claim 28 including division circuits for dividing the frequency of said output signal by a plurality of factors so that outputs having frequencies related to said fundamental frequency by any desired ratios can be obtained.

Claim 31

The system of claim 29 wherein said plurality of factors includes the integers 1, 2, 4, 6, 8, 16, and 32.

Claim 32

The system of claim 30 including: a plurality of decoders each of which is responsive to the accumulation of a respective allowable count in said first register; and means responsive to said decoders in the absence of one of said respective allowable counts for extending said period of time during which said pulses are provided to said first register until one of said respective counts is accumulated in said first register, whereby said accumulated count is restricted to one of said respective allowable counts.

Claim 33

The system of claim 31 including a subtractor for subtracting the first x of said pulses transmitted by said divider towards said first register where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said respective allowable counts.

Claim 34

The system of claim 32 including means for isolating and amplifying said input signal presented to said frequency extractor.

Claim 35

The system of claim 33 wherein said input signal comprises a continuous waveform, and including means responsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses on every nth cycle of said continuous waveform where n is any positive integer, whereby said output signal tracks said fundamental frequency of said waveform.

Claim 36

The system of claim 25 including a second frequency source connected to said second register to cause said second register to count at a rate of m times said first register, where m is the ratio of the frequency of said second frequency source to the frequency of said frequency source, whereby said output signal produced by said detector has a frequency m times said fundamental frequency.

Claim 37

Apparatus for generating an output signal having a frequency which is proportional to the fundamental frequency of an input signal having a frequency varying waveform comprising, in combination: a frequency extractor for extracting said fundamental frequency for each cycle of said waveform; a division circuit responsive to said extractor for producing a trigger pulse on every nth cycle of said waveform, where n is any integer; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said trigger pulse for generating a second control signal for initializing said first register and a first control signal having a duration proportional to said fundamental frequency of said nth cycle; a gate responsive to said first control signal for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency of said nth cycle; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control signals, whereby said accumulated count is updated every nth cycle; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output at a frequency proportional to said accumulated count; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count to said second register, whereby said output signal has a frequency which tracks said fundamental frequency of said waveform.

Claim 38

Apparatus for generating an output signal having a frequency which is proportional to the fundamental frequency of an input signal having a frequency varying waveform comprising, in combination: a frequency extractor for extracting said fundamental frequency for each cycle of said waveform; a division circuit responsive to said extractor for producing a trigger pulse on every nth cycle of said waveform, where n is any integer; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said trigger pulse for generating a second control signal for initializing said first register and a first control signal having a duration proportional to said fundamental frequency of said nth cycle; a gate responsive to said first control signal for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency of said nth cycle; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control signals, whereby said accumulated count is updated every nth cycle; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output at a frequency proportional to said accumulated count; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count to said second register, whereby said output signal has a frequency which tracks said fundamental frequency of said waveform.

Claim 39

The system of claim 15 wherein said plurality of decoders comprises twelve decoders and said respective allowable counts have specified ratios with respect to each other.

Claim 40

The system of claim 33 wherein said input signal comprises a plurality of discrete segments separated by time intervals and including means responsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses for each of said discrete segments, whereby the frequency of said output signal is proportional to said fundamental frequency of said discrete segments.

Claim 41

Apparatus for generating an output signal having a frequency proportional to the fundamental frequency of a discrete segment of an input signal including a plurality of discrete segments separated by time intervals, and sustaining said output signal until a subsequent one of said discrete segments is received by said apparatus comprising, in combination; a frequency extractor for extracting said fundamental frequency of said discrete segment; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said frequency extractor upon the receipt of each of said discrete segments for generating a second control pulse for initializing said first register and a first control pulse having a duration proportional to said fundamental frequency; a first gate responsive to said first control pulse for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control pulses, whereby said accumulated count in said storage register is updated for each of said discrete segments; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output having a frequency proportional to said accumulated count and thereby to said fundamental frequency; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count from said storage register to said second register, whereby said output signal associated with a particular one of said discrete segments is repeatedly produced until a subsequent one of said discrete sergments is received.

Claim 42

Apparatus for generating an output signal having a frequency proportional to the fundamental frequency of a discrete segment of an input signal including a plurality of discrete segments separated by time intervals, and sustaining said output signal until a subsequent one of said discrete segments is received by said apparatus comprising, in combination; a frequency extractor for extracting said fundamental frequency of said discrete segment; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said frequency extractor upon the receipt of each of said discrete segments for generating a second control pulse for initializing said first register and a first control pulse having a duration proportional to said fundamental frequency; a first gate responsive to said first control pulse for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control pulses, whereby said accumulated count in said storage register is updated for each of said discrete segments; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output having a frequency proportional to said accumulated count and thereby to said fundamental frequency; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count from said storage register to said second register, whereby said output signal associated with a particular one of said discrete segments is repeatedly produced until a subsequent one of said discrete sergments is received.

Claim 43

Apparatus in accordance with claim 39 including division circuits for dividing the frequency of said output signal by a plurality of factors, whereby signals having frequencies related to said fundamental frequency by any desired ratios can be obtained.