Electronic delay blaster

Claim 2

Electronic delay blaster for detonating blasting caps for seismic energy shaping, comprising in combination a plurality of blasting-cap circuits each having a siliconcontrolled-rectifier for passing current to detonate the cap and a control circuit for initiating said current flow, a crystal oscillator for generating a continuous series of clock pulses, an electronic flip-flop unit connected to each of said control circuits for actuating said silicon-controlled-rectifiers, first circuit means for connecting said clock pulses to an input of each of said flip-flop units for flipping same upon receipt of the first clock pulse after each unit has been enabled, an enabling input circuit for each of said flip-flop units, second circuit means for applying an enabling signal to a first one of said flip-flop units for initiating a shaped seismic charge, means for dividing said clock pulses into predetermined longer time periods between pulses, electronic circuit means for providing a selectable series of said divided pulses for selecting a predetermined delay from the beginning to the end of said series, and third circuit means associated with each of the remaining ones of said flip-flop units after said first for applying enabling signals in accordance with a preselected time delay for each.

Claim 3

Electronic delay blaster according to claim 1, wherein said dividing means comprises a series of electronic divide-by-ten units, and said electronic circuit means comprises a plurality of binary-coded-decimal units, one for each of said divide-by-ten units after the first.

Claim 4

Electronic delay blaster according to claim 2, wherein said third circuit means comprises an AND gate connected to each of said flip-flop units after the first and a plurality of decimal circuits connected to said binary-coded-decimal units with selector switches for connecting selected ones of said decimal circuits to said AND gate.

Claim 5

Electronic delay blaster according to claim 3, wherein said first circuit means includes an AND gate between said crystal oscillator and flip-flop-unit inputs, and said blaster further comprises means for closing said last-named AND gate at the end of said series of divided pulses.

Claim 6

Electronic delay blaster for seismic energy shaping, comprising in combination a plurality of blasting-cap circuits each having a silicon-controlled-rectifier connected in series with terminals for connecting a blasting cap and a control circuit for initiating said current flow through said silicon-controlled-rectifier and cap, a crystal oscillator for generating a continuous series of clock pulses at a frequency of 10 kilohertz, a solid-state electronic J-K-type flip-flop unit connected to each of said control circuits via a transformer and capacitor for actuating said silicon-controlled-rectifiers, first circuit means including an AND gate between said oscillator and a parallel circuit to inputs of said flip-flop units for flipping said units upon receipt of the first clock pulse after each unit has been enabled, a J-input circuit for each of said flip-flop units and said K-inputs being connected to a logic common, second circuit means for applying an enabling signal to the J-input of a first one of said flip-flop units for initiating a shaped seismic charge, a series of three divide-by-ten solid-state electronic units connected to said oscillator on the output side of said AND gate, solid-state electronic circuit means comprising a binary-coded-decimal unit connected to each of said second and third divide-by-ten units for providing ten circuits each for selection of predetermined delays from 0 to 99 milliseconds, third circuit means comprising a selector switch for each of said ten circuits and an AND gate all for each of said flip-flop units after said first for applying enabling signals to the J-inputs thereof, and fourth circuit means including an AND gate connected to the tenth of each of said selection circuits for providing an output to said first circuit AND gate to cut off said clock pulses from said parallel circuit at the end of 99 milliseconds after the initiation of a shaped charge by said second circuit means.

Claim 7

Electronic delay blaster for seismic energy shaping, comprising in combination a plurality of blasting-cap circuits each having a silicon-controlled-rectifier connected in series with terminals for connecting a blasting cap and a control circuit for initiating said current flow through said silicon-controlled-rectifier and cap, a crystal oscillator for generating a continuous series of clock pulses at a frequency of 10 kilohertz, a solid-state electronic J-K-type flip-flop unit connected to each of said control circuits via a transformer and capacitor for actuating said silicon-controlled-rectifiers, first circuit means including an AND gate between said oscillator and a parallel circuit to inputs of said flip-flop units for flipping said units upon receipt of the first clock pulse after each unit has been enabled, a J-input circuit for each of said flip-flop units and said K-inputs being connected to a logic common, second circuit means for applying an enabling signal to the J-input of a first one of said flip-flop units for initiating a shaped seismic charge, a series of three divide-by-ten solid-state electronic units connected to said oscillator on the output side of said AND gate, solid-state electronic circuit means comprising a binary-coded-decimal unit connected to each of said second and third divide-by-ten units for providing ten circuits each for selection of predetermined delays from 0 to 99 milliseconds, third circuit means comprising a selector switch for each of said ten circuits and an AND gate all for each of said flip-flop units after said first for applying enabling signals to the J-inputs thereof, and fourth circuit means including an AND gate connected to the tenth of each of said selection circuits for providing an output to said first circuit AND gate to cut off said clock pulses from said parallel circuit at the end of 99 milliseconds after the initiation of a shaped charge by said second circuit means.