Pulse transforming circuit arrangements using a clock pulse responsive delayed inverter means

Claim 2

A pulse transforming circuit arrangement comprising: a delayed inverting means for inverting an input pulse having a relatively long duration to produce an output pulse whose voltage level varies with a predetermined time delay from the level variation of the input pulse; at least one logic gate means coupled to said delayed inverting means to receive the output pulse of said delayed inverting means and the input pulse for producing an output pulse which is substantially a function of the level variation of the input pulse and having a shorter duration than the input pulse; and a source of clock pulses; said delayed inverting means comprising a first clock pulse responsive delayed inverting means operative to invert an input pulse according to a voltage level of at least one clock pulse, which clock pulse varies between a first voltage level during a first section of a period thereof and a second voltage level during a second section of the period following the first section, the voltage level of the input pulse varying when the clock pulse varies from the second voltage level to the first voltage level, and said clock pulse responsive inverting means being operative as an inverter to invert the input pulse when the clock pulse is at the second voltage level.

Claim 3

A pulse transforming circuit arrangement according to claim 1, wherein said first clock pulse responsive delayed inverting means comprising a clocked inverter comprising a P- and an N-channel transistor constituting a complementary inverter; and P-and N-channel transistors having their gate electrodes supplied with first and second mutually complementary clock pulses, said clocked inverter being prevented from carrying out inversion of the input signal when the first clock pulse has the first voltage level and the second clock pulse signal has the second voltage level and effecting said inversion when the first clock pulse has the second voltage level and the second clock pulse signal has the first voltage level.

Claim 4

A pulse transforming circuit arrangement according to claim 1, wherein first clock pulse responsive delayed inverting means is a clocked inverter comprising a load transistor of one channel type; an inverting transistor of the same channel type as said load transistor; and a transistor of the same channel type as said load transistor having a gate electrode supplied with the clock pulse for coupling the input signal to said inverting transistor when the clock pulse has the second voltage level.

Claim 5

A pulse transforming circuit arrangement according to claim 1, wherein said first clock pulse responsive delayed inverting means Comprises a first and a second inverter; a first transistor for coupling the input signal to the input of said first inverter through the channel of the first transistor; a second transistor for the output of the first inverter to the input of said second inverter through the channel of said second transistor; and means for coupling the output of said second inverter to the input of said first inverter, said first and second transistors having gate electrodes supplied with clock pulses so as to cause the channels of said transistors to be alternately rendered conducting.

Claim 6

A pulse transforming circuit arrangement according to claim 1, wherein said first clock pulse responsive delayed inverting means comprises a first NAND gate supplied with the clock pulse and input signal; an inverter supplied with the input signal; a second NAND gate supplied with the clock pulse and an output signal from said inverter; and a third and a fourth NAND gate each having one of the two input terminals supplied with an output signal from said first and second NAND gates respectively, the other input terminal and output terminal of said third and fourth NAND gates being crosscoupled to form a bistable circuit.

Claim 7

A pulse transforming circuit arrangement according to claim 2 further comprising means coupled to the output of said clocked inverter for preventing attenuation of output voltage level of said clocked inverter during an inoperative period thereof.

Claim 8

A pulse transforming circuit arrangement according to claim 1 further comprising synchronizing means for synchronizing the level variation of the input pulse to said first clock pulse responsive delayed inverting means with the level variation of the clock pulse, said synchronzing means including second and third clock pulse responsive delayed inverting means cascade-connected at the input side of said first clock pulse responsive delayed inverting means and receiving the input pulse, said second clock pulse responsive delayed inverting means being operative as an inverter concurrently with said first clock pulse responsive delayed inverting means; and said third clock pulse responsive delayed inverting means being operative as an inverter alternately with said first and second clock pulse responsive delayed inverting means.

Claim 9

A pulse transforming circuit arrangement according to claim 7, wherein the second and third clock pulse responsive delayed inverting means comprise clocked inverters, respectively.

Claim 10

A pulse transforming circuit arrangement according to claim 7, herein said second clock pulse responsive delayed inverting means comprises a first NAND gate supplied with a first clock pulse signal and input signal; a first inverter supplied with the input signal; a second NAND gate supplied with the first clock pulse signal and an output signal from said first inverter; and a third and a fourth NAND gate each having one of the two input terminals supplied with an output signal from said first and second NAND gates respectively, the other input terminal and output terminal of said third and fourth NAND gates being cross-coupled to comprise a first bistable circuit; and said third clock pulse responsive delayed inverting means comprises a fifth NAND gate supplied with a second clock pulse signal complementary to said first clock pulse and an output signal from said first bistable circuit; a second inverter supplied with the output signal from said first bistable circuit; a sixth NAND gate supplied with the second clock pulse and an output signal from said second inverter; and a seventh and an eighth NAND gate each having one of the two input terminals supplied with an output signal from said fifth and sixth NAND gates respectively, the other input terminal and output terminal of said seventh and eighth NAND gates being cross-coupled to form a second bistable circuit.

Claim 11

A pulse transforming circuit arrangement according to claim 8 further comprising first and second means respectively coupled to The outputs of said second and third clock pulse responsive delayed inverting means for preventing attenuation of output voltage levels of said first and second clock pulse responsive delayed inverting means during an inoperative period thereof.

Claim 12

A pulse transforming circuit arrangement according to claim 1 further comprising between said clock pulse responsive delayed inverting means and said logic gate cascade-connection of at least an inverting means and a second clock pulse responsive delayed inverting means which is operative as an inverter alternately with said first clock pulse responsive delayed inverting means to thereby obtain from said logic gate an output pulse whose duration is equal to or greater than the period of the clock pulse.

Claim 13

A pulse transforming circuit arrangement according to claim 11 further comprising means coupled to the output of said first clock pulse responsive delayed inverting means for preventing attenuation of output voltage level of said second clock pulse responsive delayed inverting means during an inoperative period thereof.

Claim 14

A pulse transforming circuit arrangement according to claim 1 wherein said logic gate comprises a clocked logic gate which is provided with at least one transistor having its gate electrode supplied with a clock pulse so as to be operative alternately with said first clock pulse responsive delayed inverting means to thereby obtain from said logic gate an output pulse whose duration is equal to the period of the clock pulse.

Claim 15

A pulse transforming circuit arrangement according to claim 13 further comprising means coupled to the output of said clocked type logic gate for preventing attenuation of the output voltage level of said clocked type logic gate during an inoperative period thereof.