US3868576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for automatic equalization
Assignee: Individual
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Filing: 1972-12-21
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Granted: 1975-02-25
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Expires: 1992-12-21
Abstract
Abstract A device for automatic equalization equipped with a large number of parallel equalizing networks having a fixed but mutually different transmission characteristics, the correct equalizing network being selected by means of an eye pattern analyzer.
Inventors
- 👤 Felix Bagdasarjanz
- 👤 Peter Eugen Leuthold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:55
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A device for automatic equalization of the transmission characteristic formed by the amplitude-versus-frequency and the phase-versus-frequency characteristic of a transmission band associated with a transmission path for the transmission of synchronous information signals, characterized in that said device comprises analog-to-digital conversion means for converting received analog signals to digital form, a plurality of parallel equalizing networks comprising a shift register to whose input said digital signals are applied and a matrix network connected to taps of the shift register and comprising weighting elements which have values defining for each equalizing network a different transmission characteristic thereby producing a plurality of different equalized signals, said device further comprising circuit means connected to the outputs of each equalizing network, a plurality of blocking stages each associated with one of said plurality of equalizing networks and coupled to said equalizing network through said circuit means, signal quality analyzing means connected to said circuit means for evaluating the quality of each of said plurality of equalized signals, said analyzer being further connected to said blocking stages and supplying a control signal to unblock one of said stages so that an equalized signal of satisfactory quality appears at the output thereof.
Claim 2
Independent Claim
196 words
A device for automatic equalization of the transmission characteristic formed by the amplitude-versus-frequency and the phase-versus-frequency characteristic of a transmission band associated with a transmission path for the transmission of synchronous information signals, characterized in that said device comprises analog-to-digital conversion means for converting received analog signals to digital form, a plurality of parallel equalizing networks comprising a shift register to whose input said digital signals are applied and a matrix network connected to taps of the shift register and comprising weighting elements which have values defining for each equalizing network a different transmission characteristic thereby producing a plurality of different equalized signals, said device further comprising circuit means connected to the outputs of each equalizing network, a plurality of blocking stages each associated with one of said plurality of equalizing networks and coupled to said equalizing network through said circuit means, signal quality analyzing means connected to said circuit means for evaluating the quality of each of said plurality of equalized signals, said analyzer being further connected to said blocking stages and supplying a control signal to unblock one of said stages so that an equalized signal of satisfactory quality appears at the output thereof.
Claim 3
Dependent Claim
37 words
A device as claimed in claim 1, wherein said circuit means further comprises a buffer store whose delay time is equal to the time required by the quality analyzer to analyze the equalized signals applied to it.
Claim 4
Dependent Claim
213 words
A device as claimed in claim 1, characterized in that the signal quality analyzer comprises a plurality of mutually identical channels corresponding to the number of equalized signals, means for applying the equalized signals successively to the channels of the quality analyzer, quantization means in each channel responsive to the instantaneous value yk of the equalized signal applied thereto for supplying reference signal zk corresponding to the estimated level of the transmitted signal, a separate difference amplifier in each channel, means for connecting the relevant equalized signal and said reference signal from the quantizing means in the same channel thereby providing an error signal value ek (yk - zk), a statistic detection device to which said error signal values are applied and of which the output voltage value varies with the quality of the input signal, means for periodically sampling the output of said statistic detection device, a store connected to said sampling means for the temporary storage of the sampled output, and a trigger circuit means having an output circuit connected to the associated blocking device for opening this blocking device to the exclusion of the other blocking devices when a common sawtooth-shaped voltage applied to the trigger circuit exceeds the voltage value applied from the store to the relevant trigger circuit.
Claim 5
Dependent Claim
73 words
A device as claimed in claim 3, characterized in that the statistic detection device provided in each of the channels of the quality analyzer comprises a multiplier means for squaring the error signal value ek applied to it, an integrator connected in cascade with the multiplier, the squared signal values e2k from the multiplier being applied to the integrator, further means for sampling the integrator once per K sample periods, the voltage value
Claim 6
Dependent Claim
78 words
A device as claimed in claim 3, characterized in that the statistic detection device provided in each of the channels of the quality analyzer comprises a rectifier stage for converting the error signal value ek applied to it into its absolute value ek , and an integrator cascaded with the rectifier stage, the absolute values ek from the rectifier being applieD to the integrator, further means for sampling the integrator once per K sample values, the voltage value
Claim 7
Dependent Claim
88 words
A device as claimed in claim 3, characterized in that the statistic detection device provided in each of the channels of the quality analyzer comprises a rectifier stage for converting the error signal value ek applied to it into its absolute value ek , a peak detector connected in cascade with the rectifier stage for determining the maximum deviation of e relative to the average value thereof occurring in an observation period of specific duration, and means for temporarily storing said maximum value of ek in said store.
References Cited (Backward Citations)
US3660761A
Cited
US3670269A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-24 | 1978-08-26 | 1979-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-24 | 1982-08-26 | 1983-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-24 | 1986-08-26 | 1987-02-25 | $7700.00 | Window Closed / Lapsed |