US3869678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple transistor microwave amplifier
Assignee: RCA Corp
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Filing: 1973-12-18
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Granted: 1975-03-04
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Expires: 1993-12-18
Abstract
Abstract An input signal from a microwave source is divided equally between a parallel arrangement of multiple transistors by an input circuit having multiple transmission line center conductors with opposite ends capacitively coupled to a reference potential. The multiple transmission line center conductors of the input circuit are arranged to provide an impedance match between the signal source impedance and the transistor complex input impedance. An output signal from the parallel arrangement of multiple transistors is summed by an output circuit having multiple transmission line center conductors with opposite ends capacitively coupled to a reference potential. The multiple transmission line center conductors of the output circuit are arranged to provide an impedance match between the transistor complex output impedance and a terminating load impedance.
Inventors
- 👤 Donald Edwin Mahoney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:41
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/602; H03F1/00; H03F1/56; H03F1/565; H03F3/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
383 words
An amplifier comprising: first, second, third, fourTh and fifth resonant lengths of transmission lines each having center conductors with opposite ends capacitively coupled to a reference potential; input circuit means having an input terminal and first and second output terminals and said first and second transmission line center conductors being respectively capacitively coupled to each other for dividing an input signal coupled to said input terminal between said output terminals with substantially equal magnitude and equal relative phase; output circuit means having first and second input terminals and an output terminal and said third and fourth transmission line center capacitively coupled to said fifth transmission line center conductor for summing input signals coupled to said first and second input terminals of said output circuit; a first semiconductor device having first, second and third terminals, an input impedance and an output impedance, said first terminal of said first device being coupled to said first output terminal of said input circuit, said second terminal of said first device being coupled to said first input terminal of said output circuit and said third terminal of said first device being coupled to said reference potential, said first and second transmission line center conductors being mutually arranged to match said first semiconductor input impedance and said third and fifth transmission line center conductors being mutually arranged to match said first semiconductor output impedance; a second semiconductor device having first, second and third terminals, an input impedance and an output impedance, said first terminal of said second device being coupled to said second output terminal of said input circuit, said second terminal of said second device being coupled to said second input terminal of said output circuit and said third terminal of said second device being coupled to said reference potential, said first and second transmission line center conductors being mutually arranged to match said second semiconductor input impedance and said fourth and fifth transmission line center conductor being mutually arranged to match said second semiconductor output impedance; means for coupling an input microwave signal to said input circuit input terminal; means for coupling a predetermined D.C. bias to said first and second semiconductor devices; and means responsive to said input microwave signal and said D.C. bias for coupling an output microwave signal from said output circuit output terminal.
Claim 2
Dependent Claim
383 words
An amplifier comprising: first, second, third, fourTh and fifth resonant lengths of transmission lines each having center conductors with opposite ends capacitively coupled to a reference potential; input circuit means having an input terminal and first and second output terminals and said first and second transmission line center conductors being respectively capacitively coupled to each other for dividing an input signal coupled to said input terminal between said output terminals with substantially equal magnitude and equal relative phase; output circuit means having first and second input terminals and an output terminal and said third and fourth transmission line center capacitively coupled to said fifth transmission line center conductor for summing input signals coupled to said first and second input terminals of said output circuit; a first semiconductor device having first, second and third terminals, an input impedance and an output impedance, said first terminal of said first device being coupled to said first output terminal of said input circuit, said second terminal of said first device being coupled to said first input terminal of said output circuit and said third terminal of said first device being coupled to said reference potential, said first and second transmission line center conductors being mutually arranged to match said first semiconductor input impedance and said third and fifth transmission line center conductors being mutually arranged to match said first semiconductor output impedance; a second semiconductor device having first, second and third terminals, an input impedance and an output impedance, said first terminal of said second device being coupled to said second output terminal of said input circuit, said second terminal of said second device being coupled to said second input terminal of said output circuit and said third terminal of said second device being coupled to said reference potential, said first and second transmission line center conductors being mutually arranged to match said second semiconductor input impedance and said fourth and fifth transmission line center conductor being mutually arranged to match said second semiconductor output impedance; means for coupling an input microwave signal to said input circuit input terminal; means for coupling a predetermined D.C. bias to said first and second semiconductor devices; and means responsive to said input microwave signal and said D.C. bias for coupling an output microwave signal from said output circuit output terminal.
Claim 3
Dependent Claim
50 words
An amplifier according to claim 1, wherein said first, second, third, fourth and fifth transmission line center conductors include respectively first, second, third, fourth and fifth coplanar conductive strips on one surface of a dielectric substrate, said substrate having a conductive surface, opposite said one surface, at said reference potential.
Claim 4
Dependent Claim
42 words
An amplifier according to claim 1, wherein said capacitive coupling of said first and second transmission line center conductors to each other includes a first relatively small gap separating said first transmission line center conductor from said second transmission line center conductor.
Claim 5
Dependent Claim
66 words
An amplifier according to claim 1, wherein said capacitive coupling of said third and fourth transmission line center conductors to said fifth transmission line center conductor includes a second relatively small gap separating said third transmission line center conductor from said fifth transmission line center conductor and a third relatively small gap separating said fourth transmission line center conductor from said fifth transmission line center conductor.
Claim 6
Dependent Claim
215 words
An amplifier comprising: a signal divider means having an input terminal and first and second output terminals, said signal divider means having first and second transmission line center conductors capacitively coupled respectively to each other and each of said first and second center conductors having opposite ends capacitively coupled to a reference Potential; a signal summing means having first and second input terminals and an output terminal, said signal summing means having third and fourth transmission line center conductors capacitively coupled to a fifth transmission line center conductor, said third, fourth and fifth transmission line center conductors each having opposite ends capacitively coupled to a reference potential; a first semiconductor device having a first terminal coupled to said signal divider first output terminal, a second terminal of said first device coupled to said first input terminal of said signal summing means and a third terminal of said first device coupled to said reference potential; a second semiconductor device having a first terminal coupled to said signal divider second output terminal, a second terminal of said second device coupled to said second input terminal of said signal summing means and a third terminal of said second device coupled to said reference potential, and; means for coupling a D.C. bias to said first and second semiconductor devices.
Claim 7
Dependent Claim
215 words
An amplifier comprising: a signal divider means having an input terminal and first and second output terminals, said signal divider means having first and second transmission line center conductors capacitively coupled respectively to each other and each of said first and second center conductors having opposite ends capacitively coupled to a reference Potential; a signal summing means having first and second input terminals and an output terminal, said signal summing means having third and fourth transmission line center conductors capacitively coupled to a fifth transmission line center conductor, said third, fourth and fifth transmission line center conductors each having opposite ends capacitively coupled to a reference potential; a first semiconductor device having a first terminal coupled to said signal divider first output terminal, a second terminal of said first device coupled to said first input terminal of said signal summing means and a third terminal of said first device coupled to said reference potential; a second semiconductor device having a first terminal coupled to said signal divider second output terminal, a second terminal of said second device coupled to said second input terminal of said signal summing means and a third terminal of said second device coupled to said reference potential, and; means for coupling a D.C. bias to said first and second semiconductor devices.
References Cited (Backward Citations)
US3371284A
Cited
US3436669A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-03 | 1978-09-02 | 1979-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-03 | 1982-09-02 | 1983-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-03 | 1986-09-02 | 1987-03-04 | $7700.00 | Window Closed / Lapsed |