Abstract A logic system for sequentially testing the states of a system of contacts: It is characterized in that it comprises: 2n p contacts to be tested, n and p being integers greater than 1, the contacts being tested by groups of 2m contacts, m being an integer less than n; a diode matrix comprising 2n columns and 2p rows wherein each diode is in series with one of the contacts to be tested, each column is embodied by a bus bar having one end connected via a load resistance to one pole of a battery whose other pole is earthed, and each row is earthed via a switching transistor called a ''''row transistor''''; 2m contact position reading circuits each comprising a diode logic or-circuit having 2n m inputs, each of the 2n bus bars being connected to just one of the latter inputs, the output of each logic or-circuit being connected via two diodes in series to the base of a transistor called ''''reading transistor'''' whose emitter is earthed and whose collector is connected to an amplifier for detecting whether the reading transistor is in the conductive or non-conductive state, each such state corresponding to one of the positions of the tested contact; and an address counter having 2n p m addresses which are decoded through the agency of the matrix and of a selector circuit comprising diode logic or-circuits having their outputs earthed via a switching transistor called ''''selecting transistor'''' and their inputs connected to the bus bars, so that during the decoding of an address the selecting circuit earths every input but one of each reading circuit and only one of the row transistors is in the conductive state.
Inventors
👤 Poland Nahon
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-08 15:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/50; G01R31/66
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
266 words
A logic circuit for testing the states of an array of contacts comprising: a. 2n p contacts to be tested, n and p being integers greater than 1, the contacts being tested by groups of 2m, m being an integer less than n; b. a diode matrix comprising 2n columns and 2p rows wherein each diode is in series with one of the contacts to be tested, each column is connected to one of a plurality of 2n bus bars, each bus bar having one end connected via a load resistance to one pole of a battery whose other pole is grounded, and each row is grounded via row switching means; c. 2m reading circuits each comprising a diode logic or-circuit having 2n m inputs and a single output, each of the 2n bus bars being connected to only one of said reading circuit inputs the output of each logic or-circuit being connected to the base of a reading transistor said reading transistor connected to an amplifier for detecting whether the reading transistor is in the conductive or non-conductive state, each such state corresponding to one of the positions of the teSted contact; d. an address counter having 2n p m addresses; and e. decoding means connected to said address counter and comprising selector circuits having diode logic or-circuit elements, said elements having outputs grounded via a selecting transistor and inputs connected to said bus bars, said decoding means grounding every input but one of each of said reading circuits and said decoding means triggering only one of said row switching means into a conducting state.
Claim 2
Dependent Claim
266 words
A logic circuit for testing the states of an array of contacts comprising: a. 2n p contacts to be tested, n and p being integers greater than 1, the contacts being tested by groups of 2m, m being an integer less than n; b. a diode matrix comprising 2n columns and 2p rows wherein each diode is in series with one of the contacts to be tested, each column is connected to one of a plurality of 2n bus bars, each bus bar having one end connected via a load resistance to one pole of a battery whose other pole is grounded, and each row is grounded via row switching means; c. 2m reading circuits each comprising a diode logic or-circuit having 2n m inputs and a single output, each of the 2n bus bars being connected to only one of said reading circuit inputs the output of each logic or-circuit being connected to the base of a reading transistor said reading transistor connected to an amplifier for detecting whether the reading transistor is in the conductive or non-conductive state, each such state corresponding to one of the positions of the teSted contact; d. an address counter having 2n p m addresses; and e. decoding means connected to said address counter and comprising selector circuits having diode logic or-circuit elements, said elements having outputs grounded via a selecting transistor and inputs connected to said bus bars, said decoding means grounding every input but one of each of said reading circuits and said decoding means triggering only one of said row switching means into a conducting state.