Digital synchronization system

Claim 2

A digital synchronizing system comprising: a first source of synchronizing pulses; a second source of synchronizing pulses which is subject to degradation; resettable counting means coupled to said first source of synchronizing pulses for counting pulses generated in said first source of synchronizing pulses and for generating a first reset pulse upon the counting of a constant number of pulses from said first source of synchronizing pulses; converting means coupled to said first source of synchronizing pulses and to said second source of synchronizing pulses for sampling the voltage level of pulses generted by said second source of synchronizing pulses at a rate determined by the rate of said first source of synchronizing pulses and for storing information representative of said sampled voltage level; gating means coupled to said converting means for monitoring said stored information in said converting means and for generating a second reset pulse when said stored information corresponds to a pulse having time duration characteristics substantially equal to the time duration characteristics of pulse components from said second source of synchronizing pulses; resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon the incidence of either one or both of said first and second reset pulses; and a deflection circuit coupled to said resettable counting means, the operation of which is synchronized by the occurrence of a pulse generated in said resettable counting means.

Claim 3

A digital synchronizing system comprising: a first source of synchronizing pulses; a second source of synchronizing pulses which is subject ot degradation; resettable counting means coupled to said first source of synchronizing pulses for counting pulses generated in said first source of synchronizing pulses and for generating a first reset pulse upon the counting of a constant number of pulses from said first source of synchronizing pulses; converting means coupled to said first source of synchronizing pulses and to said second source of synchronizing pulses for sampling the voltage level of pulses generated by said second source of synchronizing pulses at a rate determined by the rate of said first source of synchronizing pulses and for storing information representative of said sampled voltage level; gating means coupled to said converting means for monitoring said stored information in said converting means and for generating a second reset pulse when said stored information corresponds to a pulse having time duration characteristics substantially equal to the time duration characteristics of pulse components from said second source of synchronizing pulses; resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon the incidence of either one or both of said first and second reset pulses; a deflection circuit coupled to said resettable counting means, the operation of which is synchronized by the occurrence of a pulse generated in said resettable counting means; and feedback means coupled to said deflection circuit and to said resettable counting means for sensing when said deflection circuit is not properly synchronized and for generating a pulse to insure the operation of said deflection circuit, thereby protecting said deflection circuit from malfunction.

Claim 4

A digital synchronizing system comprising: a first source of synchronizing pulses; a second source of synchronizing pulses which is subject ot degradation; resettable counting means coupled to said first source of synchronizing pulses for counting pulses generated in said first source of synchronizing pulses and for generating a first reset pulse upon the counting of a constant number of pulses from said first source of synchronizing pulses; converting means coupled to said first source of synchronizing pulses and to said second source of synchronizing pulses for sampling the voltage level of pulses generated by said second source of synchronizing pulses at a rate determined by the rate of said first source of synchronizing pulses and for storing information representative of said sampled voltage level; gating means coupled to said converting means for monitoring said stored information in said converting means and for generating a second reset pulse when said stored information corresponds to a pulse having time duration characteristics substantially equal to the time duration characteristics of pulse components from said second source of synchronizing pulses; resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon the incidence of either one or both of said first and second reset pulses; a deflection circuit coupled to said resettable counting means, the operation of which is synchronized by the occurrence of a pulse generated in said resettable counting means; and feedback means coupled to said deflection circuit and to said resettable counting means for sensing when said deflection circuit is not properly synchronized and for generating a pulse to insure the operation of said deflection circuit, thereby protecting said deflection circuit from malfunction.

Claim 5

A digital synchronizing system according to claim 2 wherein said resettable counting means comprises a serial combination of a plurality of flip-flops with a common resetting line, the output terminals of said flip-flops which sense the constant count being coupled to logic circuitry which produces an enabling pulse for resetting all of said flip-flops.

Claim 6

A digital synchronizing system according to claim 3 wherein: said converting means comprises a serial-to-parallel converter consisting of a shift register.

Claim 7

A digital synchronizing system according to claim 4 wherein: said gating means comprises a coincidence gate.

Claim 8

A digital synchronizing system according to claim 5 wherein: said resetting means comprises at least one logic gate which induces a resetting level on the common resetting line of said resettable counting means upon the occurrence of the enabling pulse for resetting the flip-flops of said resettable counting means or upon the occurrence of a coincidence condition upon said coincidence gate.

Claim 9

In a television receiver, a digital deflection synchronizing system comprising: a deflection generator and amplifier for producing deflection waveforms; a deflection winding coupled to said deflection amplifier; a source of clock synchronizing pulses; a source of deflection rate synchronizing pulses; resettable counting means coupled to said deflection amplifier and to said source of clock synchronizing pulses for counting a series of said clock synchronizing pulses and producing a deflection cycle synchronizing pulse for synchronizing said deflection amplifier; converting means coupled to said source of deflection rate synchronizing pulses for sampling and storing information representative of said deflection rate synchronizing pulses at said clock synchronizing pulse rate; gating means coupled to said converting means for passing information representative of said deflection rate synchronizing pulses; and resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon energization by either or both of said gating means and said resettable counting means.

Claim 10

In a television receiver, a digital deflection synchronizing system comprising: a deflection generator and amplifier for producing deflection waveforms; a deflection winding coupled to said deflection amplifier; a source of clock synchronizing pulses; a source of deflection rate synchronizing pulses; resettable counting means coupled to said deflection amplifier and to said source of clock synchronizing pulses for counting a series of said clock synchronizing pulses and producing a deflection cycle synchronizing pulse for synchronizing said deflection amplifier; converting means coupled to said source of deflection rate synchronizing pulses for sampling and storing information representative of said deflection rate synchronizing pulses at said clock synchronizing pulse rate; gating means coupled to said converting means for passing information representative of said deflection rate synchronizing pulses; and resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon energization by either or both of said gating means and said resettable counting means.

Claim 11

In a television receiver, a digital deflEction synchronizing system comprising: a deflection generator and amplifier for producing deflection waveforms; a deflection winding coupled to said deflection amplifier; a source of clock synchronizing pulses; a source of deflection rate synchronizing pulses; resettable counting means coupled to said deflection amplifier and to said source of clock synchronizing pulses for counting a series of said clock synchronizing pulses and for producing a deflection cycle synchronizing pulse for synchronizing said deflection amplifier; converting means coupled to said source of deflection rate synchronizing pulses for sampling and storing information representative of said deflection rate synchronizing pulses at said clock synchronizing pulse rate; gating means coupled to said converting means for passing information representative of said deflection rate synchronizing pulses; resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon energization by either or both of said gating means and said resettable counting means; and feedback means coupled to said deflection amplifier for sensing said deflection waveforms and for producing correcting signals for said deflection amplifier when said deflection amplifier is not synchronized by said deflection cycle synchronizing pulse.

Claim 12

In a television receiver, a digital deflEction synchronizing system comprising: a deflection generator and amplifier for producing deflection waveforms; a deflection winding coupled to said deflection amplifier; a source of clock synchronizing pulses; a source of deflection rate synchronizing pulses; resettable counting means coupled to said deflection amplifier and to said source of clock synchronizing pulses for counting a series of said clock synchronizing pulses and for producing a deflection cycle synchronizing pulse for synchronizing said deflection amplifier; converting means coupled to said source of deflection rate synchronizing pulses for sampling and storing information representative of said deflection rate synchronizing pulses at said clock synchronizing pulse rate; gating means coupled to said converting means for passing information representative of said deflection rate synchronizing pulses; resetting means coupled to said gating means and to said resettable counting means for resetting said resettable counting means upon energization by either or both of said gating means and said resettable counting means; and feedback means coupled to said deflection amplifier for sensing said deflection waveforms and for producing correcting signals for said deflection amplifier when said deflection amplifier is not synchronized by said deflection cycle synchronizing pulse.

Claim 13

A digital deflection synchronization system according to claim 8 wherein: filtering means are coupled serially between said source of deflection rate synchronizing pulses and said converting means for filtering signals which do not have the width characteristic of said deflection rate synchronizing pulses which may be interposed among said deflection rate synchronizing pulses so that sampled information representative of said filtered signals does not pass through said gating means and said resetting means to reset said resettable counting means.

Claim 14

A digital deflection synchronization system according to claim 9 wherein: a pulse shaping circuit comprising a monostable multivibrator is coupled between said resettable counting means and said deflection amplifier.

Claim 15

A digital deflection synchronization system according to claim 10 wherein said filtering means comprises: a low pass filter circuit coupled to said source of deflection rate synchronizing pulses; a peak detecting circuit for generating signals representative of the presence of said deflection rate synchronizing pulses by generating a rapid change in voltage level when said deflection rate synchronizing pulses are present which slowly decays over the period when said deflection rate synchronizing pulses are not present coupled to said source of deflection rate synchronizing pulses; and a comparing circuit coupled to between said low pass filter circuit and said detecting circuit and said converting means for comparing signals representative of output voltage from said low pass filter to signals representative of output voltage from said peak detecting circuit and generating difference input signals to said converting means when said deflection rate synchronizing pulses are present.