US3878370A
Expired / Lapsed
US
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Electronic interval timer
Assignee: ARTRONICS CORP
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Filing: 1973-09-04
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Granted: 1975-04-15
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Expires: 1993-09-04
Abstract
Abstract An electronic interval timer with an input means for setting an interval and a trigger switch for starting the timer. Actuating the trigger switch loads a number representing the interval into a register and clears a counter. Subsequent clock pulses pass through an enabled gating circuit and advance the counter. A comparator energizes an output circuit until the values in the counter and the register are equal. While the output circuit is energized, the trigger switch is disabled and operation of the input means does not affect the timer.
Inventors
- 👤 Anthony Santomango
- 👤 Jr Nicholas N Hatheway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:18
CPC Classifications
H; H01; H01H; H01H43/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
203 words
An interval timing unit with a source of clock pulses, a counter for transmitting signals representing an interval being timed, a register for transmitting time interval signals representing a number stored therein corresponding to the interval to be timed, a comparator connected to receive signals from the counter and register, the comparator including means for transmitting first and second signals when the counter and register signals are unequal other than equal and, respectively, and output means energized in response to the first signal, the improvement of a starting circuit comprising: a switch means; means connected to the comparator and said switch means for generating a trigger pulse when said switch means is actuated while the comparator transmits the second signal; input gating means for coupling, in response to an enabling signal, clock pulses from the source to the counter whereby the signals from the counter are altered periodically; and an enabling circuit for transmitting the enabling signal to said gating means, said enabling circuit including means responsive to a first clock pulse after said trigger pulse generating means transmits a trigger pulse for clearing the counter, thereby causing the comparator to transmit the first signal and thereby enabling the counter to begin counting.
Claim 2
Dependent Claim
203 words
An interval timing unit with a source of clock pulses, a counter for transmitting signals representing an interval being timed, a register for transmitting time interval signals representing a number stored therein corresponding to the interval to be timed, a comparator connected to receive signals from the counter and register, the comparator including means for transmitting first and second signals when the counter and register signals are unequal other than equal and, respectively, and output means energized in response to the first signal, the improvement of a starting circuit comprising: a switch means; means connected to the comparator and said switch means for generating a trigger pulse when said switch means is actuated while the comparator transmits the second signal; input gating means for coupling, in response to an enabling signal, clock pulses from the source to the counter whereby the signals from the counter are altered periodically; and an enabling circuit for transmitting the enabling signal to said gating means, said enabling circuit including means responsive to a first clock pulse after said trigger pulse generating means transmits a trigger pulse for clearing the counter, thereby causing the comparator to transmit the first signal and thereby enabling the counter to begin counting.
Claim 3
Dependent Claim
41 words
A timing circuit as recited in claim 1, additionally comprising means for generating the time interval signals, said enabling circuit additionally comprising means responsive to said clearing means for coupling the signals from the time interval signal generator to the register.
Claim 4
Dependent Claim
91 words
A timer as recited in claim 1, wherein said enabling circuit comprises: a clocked flip-flop with a first input connected to said input gating means for setting said flip-flop in response to a trigger pulse and a second input for receiving clock pulses, said flip-flop being reset in response to each clock pulse in the absence of a signal at the first input; and means responsive to a clock pulse when said clocked flip-flop is set for clearing the counter and enabling the counter gate upon completion of the clock pulse.
Claim 5
Dependent Claim
43 words
A timing circuit as recited in claim 3, additionally comprising switching means for generating time interval signals and input gating means for the regiSter, said enabling circuit additionally comprising an inverter connected to said clock clearing means for enabling said input gating means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-14 | 1978-10-14 | 1979-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-14 | 1982-10-14 | 1983-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-14 | 1986-10-14 | 1987-04-15 | $7700.00 | Window Closed / Lapsed |