US3881156A
Expired / Lapsed
US
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Electronic timer with recirculating memory and counter for incrementing the memory
Assignee: TELE RESOURCES Inc
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Filing: 1974-09-12
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Granted: 1975-04-29
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Expires: 1994-09-12
Abstract
Abstract An electronic timer includes a recirculating memory in which binary timer numbers can be recorded and a counter for incrementing the timer number when required as it recirculates. A comparator receives the output of the timer number and a time base signal of varying polarity. A gate means responsive to the output of the comparator causes the counter to increase the timer number each time the phase of the time base signal changes. When the timer number reaches a predetermined magnitude, a time elapse gate so indicates. Various time base signals having different pulse rates may be selected, depending upon the interval to be measured. This timer may be incorporated in a telephony exchange in which the timer memory is part of the connection memory.
Inventors
- 👤 Herman Deutsch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:50
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/561; H04M3/58; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
89 words
A timer comprising a recirculating memory in which binary timer numbers can be recorded, counter means for periodically incrementing each recorded number once during each recirculation of the memory, means for supplying a time base signal of changing polarity, comparator means for comparing the low order bit of each recorded binary number to the phase of the time base signal supplied, and gate means responsive to the comparator means for causing the counter means to increase the timer number each time the phase of the time base signal changes.
Claim 2
Dependent Claim
89 words
A timer comprising a recirculating memory in which binary timer numbers can be recorded, counter means for periodically incrementing each recorded number once during each recirculation of the memory, means for supplying a time base signal of changing polarity, comparator means for comparing the low order bit of each recorded binary number to the phase of the time base signal supplied, and gate means responsive to the comparator means for causing the counter means to increase the timer number each time the phase of the time base signal changes.
Claim 3
Dependent Claim
18 words
The timer of claim 1, wherein said temporary memory comprises a plurality of equal length synchronized shift registers.
Claim 4
Dependent Claim
107 words
A timer comprising a recirculating temporary memory in which a plurality of binary timer numbers can be recorded, means for reading the low order bit of each timer number as the temporary memory recirculates, time base meAns for supplying a plurality of time base signals each of which changes polarity at a different rate, selector means for selecting a time base signal to be compared with each binary number, comparator means for comparing the phase, the low order bit of each timer number with its selected time base signal, and incrementing gate means for increasing each binary number each time its selected time base signal changes polarity.
Claim 5
Dependent Claim
107 words
A timer comprising a recirculating temporary memory in which a plurality of binary timer numbers can be recorded, means for reading the low order bit of each timer number as the temporary memory recirculates, time base meAns for supplying a plurality of time base signals each of which changes polarity at a different rate, selector means for selecting a time base signal to be compared with each binary number, comparator means for comparing the phase, the low order bit of each timer number with its selected time base signal, and incrementing gate means for increasing each binary number each time its selected time base signal changes polarity.
Claim 6
Dependent Claim
23 words
The timer of claim 3, further comprising elapse gate means for producing an indication that a timer member has reached a predetermined magnitude.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-28 | 1978-10-28 | 1979-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-28 | 1982-10-28 | 1983-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-28 | 1986-10-28 | 1987-04-29 | $7700.00 | Window Closed / Lapsed |