Fractional frequency dividers

Claim 2

A frequency divider which comprises a counter circuit formed of one or more cascade connected binary counter units and supplied with an input clock pulse; a reset pulse supply means connected to the counter circuit so as to clear the contents of the counter circuit when it counts a prescribed number of input clock pulses; a polarity reversing device connected to the reset pulse supply means so as to reverse the polarity of input clock pulses delivered to the counter circuit upon receipt of a reset pulse from said reset pulse supply means, thereby attaining frequency division in the ratio or fraction whose numerator is 2 and whose denominator is an odd number.

Claim 3

A frequency divider according to claim 1 wherein the polarity reversing device comprises a binary memory device connected to the reset pulse supply means so as to have the polarity of outputs from said memory device reversed when supplied with a reset pulse from the reset pulse generator; and a logic circuit for supplying a clock pulse having the same polarity as the input clock pulse to the counter circuit upon receipt of an output from the first output terminal of the binary memory device and also supplying the counter circuit with a clock pulse having a polarity reversed from the input clock pulse upon receipt of an output from the second output terminal of the binary memory device.

Claim 4

A frequency divider according to claim 1 wherein the binary counter unit or units constituting the counter circuit consist of flip-flop circuits.

Claim 5

A frequency divider according to claim 1 wherein the reset pulse generator is an AND circuit supplied with a clock pulse delivered from the input and output terminals of the binary counter unit or units.

Claim 6

A frequency divider according to claim 1 wherein the reset pulse supply means is a NOR circuit supplied with a clock pulse given forth from the input and output terminals of the binary counter unit or units.

Claim 7

A freqeuncy divider according to claim 1 wherein the reset pulse supply means is a NAND circuit supplied with a clock pulse produced from the input and output terminals of the binary counter unit or units.

Claim 8

A freqeuncy divider according to claim 1 wherein the reset pulse supply means is an OR circuit supplied with a clock pulse transmitted from the input and output terminals of the binary counter unit or units.

Claim 9

A frequency divider according to claim 2 wherein thE binary memory device consists of flip-flop circuits.

Claim 10

A frequency divider according to claim 2 wherein the logic circuit comprises a first AND circuit for receiving a first outpt signal from the binary memory device and an input clock pulse and supplying the counter circuit with said clock pulse having the same polarity as said input clock pulse; a second AND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with said clock pulses having the same polarity as said polarity reversed input clock pulse; and an OR circuit selectively supplied with an output signal from either of the first and second AND circuits.

Claim 11

A frequency divider according to claim 2 wherein the logic circuit comprises a first NAND circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with said clock pulse having the same polarity as said input clock pulse; a second NAND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with said clock pulse having the same polarity as said polarity reversed intput clock pulse; and a third NAND circuit selectively supplied with an output signal from either of the first and second NAND circuits.

Claim 12

A frequency divider according to claim 2 wherein the logic circuit comprises a first NOR circuit for reversing a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with said clock pulse having the same polarity as said input clock pulse; a second NOR circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with said clock pulse having the same polarity as said polarity reversed input clock pulse; and a third NOR circuit selectively supplied with an output signal from either of the first and second NOR circuits.

Claim 13

A frequency divider according to claim 2 wherein the logic circuit comprises a first NAND circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with said clock pulse having the same polarity as said input clock pulse; a second NAND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with said clock pulse having the same polarity as said polarity reversed input clock pulse; and an AND circuit selectively supplied with an output signal from either of the first and second NAND circuits.

Claim 14

A frequency divider according to claim 2 wherein the logic circuit comprises a first NOR circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with said clock pulse having the same polarity as said input clock pulse; a second NOR circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with said clock pulse having the same polarity as said polarity reversed input clock pulse; and an OR circuit selectively supplied with an output from either of the first and second NOR circuits.

Claim 15

A freqeuncy divider which comprises a counter circuit consisting or one or more cascade binary counter units and supplied with an input clock pulse; a device for receiving an output clock pulse from the counter circuit and reversing the polarity of said input clock pulse.

Claim 16

A freqeuncy divider which comprises a counter circuit consisting or one or more cascade binary counter units and supplied with an input clock pulse; a device for receiving an output clock pulse from the counter circuit and reversing the polarity of said input clock pulse.

Claim 17

A frequency divider according to claim 14 wherein the polarity reversing device comprises a binary memory device carrying out polarity reversion upon receipt of an output signal from the last stage binary counteR unit; and a logic circuit for receiving an output signal from the first output terminal of said binary memory device and supplying a clock pulse having the same polarity as the input clock pulse to the counter circuit and also for receiving an output signal from the second output terminal of said binary memory device and supplying the counter circuit with a clock pulse having an opposite polarity to said clock pulse.

Claim 18

A frequency divider according to claim 14 wherein the binary counter unit or units constituting the counter circuit are flip-flop circuits.

Claim 19

A frequency divider according to claim 15 wherein the binary memory device is a flip-flop circuit.

Claim 20

A frequency divider according to claim 15 wherein the logic circuit comprises a first AND circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with a clock pulse having the same polarity as said input clock pulse; a second AND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with a clock pulse having the same polarity as said polarity reversed input clock pulse; and an OR circuit selectively supplied with an output from either of the first and second AND circuits.

Claim 21

A frequency divider according to claim 15 wherein the logic circuit comprises a first NAND circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with a clock pulse having the same polarity as said input clock pulse; a second NAND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through inverter and supplying the counter circuit with a clock pulse having the same polarity as said polarity reversed input clock pulse; and a third NAND circuit selectively supplied with an output from either of the first and second NAND circuits.

Claim 22

A frequency divider according to claim 15 wherein the logic circuit comprises a first NOR circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with a clock pulse having the same polarity as said input clock pulse; a second NOR circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with a clock pulse having the same polarity as said polarity reversed input clock pulse; and a third NOR circuit selectively supplied with an output from either of the first and second NOR circuits.

Claim 23

A frequency divider according to claim 15 wherein the logic circuit comprises a first NAND circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with a clock pulse having the same polarity as said input clock pulse; a second NAND circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with a clock pulse having the same polarity as said polarity reversed input clock pulse; and an AND circuit selectively supplied with an output from either of the first and second NAND circuits.

Claim 24

A frequency divider according to claim 15 wherein the logic circuit comprises a first NOR circuit for receiving a first output signal from the binary memory device and an input clock pulse and supplying the counter circuit with a clock pulse having the same polarity as said input clock pulse; a second NOR circuit for receiving a second output signal from the binary memory device and a polarity reversed input clock pulse through an inverter and supplying the counter circuit with a clock pulse having the same polarity as said polarity reversed input clock pulse; and an OR circuit selectively suPplied with an output from either of the first and second NOR circuits.