US3896388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing signal generator device
Assignee: Hitachi Ltd
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Filing: 1973-06-13
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Granted: 1975-07-22
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Expires: 1993-06-13
Abstract
Abstract A synchronizing signal generator device wherein a frequency divider circuit section is split into a plurality of ring counters. A reference signal having a reference frequency is applied to the first stage of the ring counter. An output signal of each ring counter is fed to the succeeding stage of the ring counter as a synchronizing pulse signal. The frequency-divided signals of predetermined frequencies as derived from the ring counters have substantially no delay over the reference signal.
Inventors
- 👤 Yoshikazu Hatsukano
- 👤 Shunji Shimada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:30
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093; H04; H04N; H04N5/00; H04N5/04; H04N5/06
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
179 words
A synchronizing signal generator device comprising: at least a first and a second ring counter, each of which includes a plurality of synchronous delay type memory circuit elements each memory circuit element having a clock input terminal for receiving synchronizing pulses and input and output terminals by which said elements are coupled in cascade; and logic gate circuit means having a plurality of input terminals coupled to said output terminals of a plurality of said elements and an output terminal coupled to the input terminal of the first element; means for applying a reference signal in common to each clock input terminal of said first ring counter in the form of synchronizing pulses; and means for connecting the output terminal of the last element of said first ring counter in common to each clock input terminal of said second ring counter in the form of synchronizing pulses; whereby a second signal of a predetermined frequency different from the frequency of said reference signal and having substantially no delay over said reference signal is derived from said second ring counter.
Claim 2
Dependent Claim
179 words
A synchronizing signal generator device comprising: at least a first and a second ring counter, each of which includes a plurality of synchronous delay type memory circuit elements each memory circuit element having a clock input terminal for receiving synchronizing pulses and input and output terminals by which said elements are coupled in cascade; and logic gate circuit means having a plurality of input terminals coupled to said output terminals of a plurality of said elements and an output terminal coupled to the input terminal of the first element; means for applying a reference signal in common to each clock input terminal of said first ring counter in the form of synchronizing pulses; and means for connecting the output terminal of the last element of said first ring counter in common to each clock input terminal of said second ring counter in the form of synchronizing pulses; whereby a second signal of a predetermined frequency different from the frequency of said reference signal and having substantially no delay over said reference signal is derived from said second ring counter.
Claim 3
Dependent Claim
29 words
The synchronizing signal generator device according to claim 1, comprising logical circuit means for forming of said second signal at least a third signal synchronized with said reference signal.
Claim 4
Dependent Claim
121 words
The synchronizing signal generator device according to claim 1, further iNcluding a third ring counter including a plurality of synchronous delay type memory circuit elements each memory circuit element having clock input terminals for receiving synchronizing pulses and input and output terminals by which said elements are coupled in cascade, and additional logic gate circuit means having a plurality of input terminals coupled to said output terminals of a plurality of said elements and an output terminal coupled to the input terminal of the first element and means for connecting the output terminal of the last element of said second ring counter in common to said each clock input terminal of said third ring counter in the form of synchronizing pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-21 | 1979-01-20 | 1979-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-21 | 1983-01-20 | 1983-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-21 | 1987-01-20 | 1987-07-22 | $7700.00 | Window Closed / Lapsed |