Digital telecommunications apparatus having error-correcting facilities

Claim 2

Multiplexing and encoding apparatus which comprises: input connection means comprising n separate input lines for accepting information bit-signals in parallel from n distinct channels; first encoder means connected to a subset of k1 of the said n input lines, for deriving (n-k1) check-bit signals from any set of k1 information-bit signals occurring one on each of the lines of the said subset, according to a first predetermined systematic block code; second encoder means connected to a subset of k2 of the said n input lines, for deriving (n-k2) check-bit signals from any set of k2 information-bit signals occurring one on each of the lines of the said subset, according to a second predetermined systematic block code; and output means for applying the information-bit signals and check-bit signals from any selected encoder means to an output channel; wherein n>k1>k2>0, and the said predetermined block codes have a common block length n.

Claim 3

Multiplexing and encoding apparatus as claimed in claim 1 wherein n 11, k1 7, k2 4, the said first predetermined systematic block code is an (11, 7, 1) code, and the said second predetermined systematic block code is an (11, 4, 2) code.

Claim 4

Multiplexing and encoding apparatus as claimed in claim 1 wherein n 11, said apparatus comprising an encoder means connected to two of the said n input lines for deriving 9 check-bit signals from any pair of information-bit signals occurring one on each of the said two input lines according to a predetermined (11, 2, 3) systematic block code.

Claim 5

Multiplexing and encoding apparatus as claimed in claim 1 and also comprising another encoder means which provides a connection from one of the said input lines via the output means to the output channel, for duplicating each signal occurring on the third one of the input lines n times on the output channel in which (n - 1) duplications are provided as check signals.

Claim 6

Multiplexing and encoding apparatus as claimed in claim 1 wherein the said first predetermined systematic block code is selected from the set of codes comprising the code having the parity-check matrix 10000010110 01000101011 00101001101 00011110001 and all substantially equivalent codes.

Claim 7

Multiplexing and encoding apparatus as claimed in claim 1 wherein one of the said predetermined systematic block codes is selected from the set of codes comprising the code having the parity-check matrix 10000001110 01000001101 00100001010 00010001001 00001000110 00000100101 00000010011 and all substantially equivalent codes.

Claim 8

Multiplexing and encoding apparatus as claimed in claim 1 wherein one of the said predetermined systematic block codes is selected from the set of codes comprising the code having the parity-check matrix 10000000001 01000000001 00100000001 00010000010 00001000010 00000100010 00000100010 00000010011 00000001011 and all substantially equivalent codes.

Claim 9

Multiplexing and encoding apparatus as claimed in claim 2 wherein the said n input lines being numbered 0, 1, 2, . . . (n-1) reSpectively and the information-bit signals occurring on the input lines being correspondingly represented by symbols do, d1, d2, . . . . dn 1, the first encoder means comprises modulo-2 adders and connection means operative to derive check-bit signals c1, c2, c3, c4 according to the equations c4 d4 + d2 +d1 c3 d5 + d3 + d1 + do c2 d6 + d3 + d2 + do c1 d6 + d5 + d4 + do and connection means for applying the check-bit signals c1 to c4 and the information-bit signals do to d6 to the output means.

Claim 10

Multiplexing and encoding apparatus as claimed in claim 8 and wherein the second encoder means comprises modulo -2 adders and connection means operative to derive check-bit signals c1 to c7 according to the equations c7 d3 + d2 + d1 c6 d3 + d2 + do c5 d3 + d1 c4 d3 + do c3 d2 + d1 c2 d2 + do c1 d1 + do and connection means for applying the check-bit signals c1 to c7 and the information-bit signals do to d3 to the output means.

Claim 11

Multiplexing and encoding apparatus as claimed in claim 9 comprising a third encoder means which comprises modulo-2 adders and connection means operative to derive check-bit signals c1 to c9 according to the equations c1 c2 c3 do + d1 c4 c5 c6 d1 c7 c8 c9 do connection means for applying the check-bit signals c1 to c9 and the information-bit signals do and d1 to the output means, and a further encoder means which includes a connection for applying the information-bit signal do to the output means.

Claim 12

Demultiplexing and decoder apparatus which comprises: output connection means comprising n separate output lines for applying decoded and corrected information-bit signals to n distinct channels; demultiplexing means for applying signals received in distinct bit-signal positions of a multiplex transmission format to n separate data lines; first decoder means for decoding and correcting errors in sets of n bit-signals occurring concurrently one on each of the said n data lines of the said demultiplexing means, according to a first predetermined systematic (n, k1, t) block code, and for applying the k1 correct and corrected information-bit signals thereof to a subset comprising k1 predetermined ones of the said n separate output lines of the output connection means; second decoder means for decoding and correcting errors in sets of n bit-signals occurring concurrently one on each of the said n data lines of the said demultiplexing means, according to a second predetermined systematic (n, k2, t) block code, and for applying the k2 correct and corrected information-bit signals thereof to a subset comprising k2 predetermined ones of the said n separate output lines of the output connection means; and control means for rendering any selected one of the encoder means operative to respond to the signals on the said n data lines and to apply correct and corrected information-bit signals to at least some of the said n separate output lines of the output connection means; wherein n>k1>k2>0 and the said predetermined systematic block codes have a common block length n.

Claim 13

Demultiplexing and decoder apparatus which comprises: output connection means comprising n separate output lines for applying decoded and corrected information-bit signals to n distinct channels; demultiplexing means for applying signals received in distinct bit-signal positions of a multiplex transmission format to n separate data lines; first decoder means for decoding and correcting errors in sets of n bit-signals occurring concurrently one on each of the said n data lines of the said demultiplexing means, according to a first predetermined systematic (n, k1, t) block code, and for applying the k1 correct and corrected information-bit signals thereof to a subset comprising k1 predetermined ones of the said n separate output lines of the output connection means; second decoder means for decoding and correcting errors in sets of n bit-signals occurring concurrently one on each of the said n data lines of the said demultiplexing means, according to a second predetermined systematic (n, k2, t) block code, and for applying the k2 correct and corrected information-bit signals thereof to a subset comprising k2 predetermined ones of the said n separate output lines of the output connection means; and control means for rendering any selected one of the encoder means operative to respond to the signals on the said n data lines and to apply correct and corrected information-bit signals to at least some of the said n separate output lines of the output connection means; wherein n>k1>k2>0 and the said predetermined systematic block codes have a common block length n.

Claim 14

Demultiplexing and decoder apparatus as claimed in claim 11 wherein n 11, k1 7, k2 4, the said first predetermined systematic block code is an (11, 7, 1) code, and the said second predetermined systematic block code is an (11, 4, 2) code.

Claim 15

Demultiplexing and decoder apparatus as claimed in claim 11 comprising a decoder means for decoding and correcting errors in sets of n bit-signals occurring concurrently one on each of the said n data lines of the said demultiplexing means, according to a predetermined systematic (11, 2, 3) block code and for applying the two correct and corrected information-bit signals thereof to a subset comprising two of the said n separate output lines of the output connection means.

Claim 16

Demultiplexing and decoder apparatus as claimed in claim 11 and also comprising another decoder means which comprises a majority voting circuit connected to the said n data lines and responsive to any signal occurring on a majority of the said n data lines.

Claim 17

Demultiplexing and decoder apparatus as claimed in claim 11 wherein the said first predetermined systematic block code is selected from the set of codes comprising the code having the parity-check matrix 10000010110 01000101011 00101001101 00011110001 and all substantially equivalent codes.

Claim 18

Demultiplexing and decoder apparatus as claimed in claim 11 wherein the said second predetermined systematic block code is selected from the set of codes comprising the code having the parity-check matrix 10000001110 01000001101 00100001010 00010001001 00001000110 00000100101 00000010011 and all substantially equivalent codes.

Claim 19

Demultiplexing and decoder apparatus as claimed in claim 11 wherein the said second predetermined systematic block code is selected from the set of codes comprising the code having the parity-check matrix 10000000001 01000000001 00100000001 00010000010 00001000010 00000100010 00000010011 00000001011 00000000111 and all substantially equivalent codes.

Claim 20

Demultiplexing and decoder apparatus as claimed in claim 15 wherein the n data lines being numbered from 0, 1, 2 . . . . (n -1) respectively and the bit-signals occurring on them being correspondingly represented by symbols eo, e1, e2, . . . . en 1, the first decoder means comprises: modulo-2 adders connected to derive syndrome-bit signals according to the equations So e10 + e4 + e2 + e1 S1 e9 + e5 + e3 + e1 + eo S2 e8 + e6 + e3 + e2 + eo S3 e7 + e6 + e5 + e4 + eo seven error detector means connected to the outputs of the modulo-2 adders and responsive to the syndromes 0111, 1100, 1010, 0110, 1001, 0101, and 0011, respectively; and seven correction means each connected to receive a separate one of the signals eo to e6 and any output from an associated one of the error detector means for complementing erroneous signals indicated by the corresponding syndromes.

Claim 21

Demultiplexing and decoder apparatus as claimed in claim 16 wherein the said n data lines being numbered 0, 1, 2 . . . (n -1) respectively and the bit-signals occurring on them being correspondingly represented by symbols eo, e1, e2 . . . en 1, the second decoder means comprises: modulo-2 adders connected to derive syndrome-bit signals and combinations thereof according to the equations So e10 + e3 + e2 + e1 S1 e9 + e3 + e2 + eo S2 e8 + e3 + e1 S3 e7 + e3 + eo S4 e6 + e2 + e1 S5 e5 + e2 + eo S6 e4 + e1 + eo S1 + S2 + S4 e9 + e8 + e6 + eo S3 + S5 e10 + e7 + e5 + e1 So + S2 e10 + e8 + e2 S1 + S3 e9 + e7 + e2 So + S4 e10 + e6+ e3 S1 + S5 e9 + e5 + e3 first voting circuit means responsive to combinations of the syndrome-bit signals which make any three of the signals S6, S5, S3 and (S1 + S2 + S4) equal to 1; second voting circuit means responsive to combinations of the syndrome-bit signals which make any three of the signals S2, S4, S6 and (So + S3 + S5) equal to 1; third voting circuit means responsive to combinations of the syndrome-bit signals which make any three of the signals S4, S5, (So + S2), and (S1 + S3) equal to 1; fourth voting circuit means responsive to combinations of the syndrome-bit signals which make any three of the signals S2, S3, (So +S4), and (S1 +S5) equal to 1; first correction means having inputs connected to receive the signal eo and the output from the first voting circuit means for correcting any error in eo indicated by the output of the first voting circuit means; second correction means having inputs connected to receive the signal e1 and the output from the second voting circuit means for correcting any error in e1 indicated by the output of the second voting circuit means; third correction means having inputs connected to receive the signal e2 and the output from the third voting circuit means for correcting any error in e2 indicated by the output of the third voting circuit means; and fourth correction means having inputs connected to receive the signal e3 and the out0ut from the fourth voting circuit means for correcting any error in e3 indicated by the output of the fourth voting circuit means.

Claim 22

Demultiplexing and decoder apparatus as claimed in claim 13 wherein, the said n data lines being numbered 0, 1, 2 . . . (n-1) respectively and the bit-signals occurring on them being correspondingly represented by symbols eo, e1, e2 . . en 1, the said decoder means comprises: modulo-2 adders connected to derive syndrome-bit signals and combinations thereof according to the equations So e10+e0 S1 e9 +eo S1 e8 + eo S3 e7 +e1 S4 e6 +e1 S5 e5 +e1 S6 e4 +e1 + eo S7 e3 +e1 + Eo S8 e2 +e1 + eo S5 + S8 e5 + e2 + eo S4 + S7 e6 + e3 + eo S3 + S6 e7 + e4 + eo S2 + S8 e8 + e2 + e1 S1 + S7 e9 + e3 + e1 So + S6 e10 + e4 + e1 first voting circuit means responsive to combinations of the syndrome-bit signals which make any four of the signals So, S1, S2, (S5 + S8), (S4+ S7), and (S3 + S6) 1; second voting circuit means responsive to combinations of the syndrome-bit signals which make any four of the signals S3, S4, S5, (S2 + S8), (S1 + S7) and (So + S6) 1; first correction means having inputs connected to receive the signal eo and the output from the first voting circuit means for correcting any error in eo indicated by the first voting cirucit means; and second correction means having inputs connected to receive the signal e1 and the output of the second voting circuit means for correcting any error in e1 indicated by the second voting circuit means.