Semiconductor block-oriented read/write memory

Claim 1

A digital memory system comprising an array of variable threshold insulated gate field effect memory transistors each having source, drain and gate electrodes and being arranged in 2n blocks and m word columns on a common substrate. said memory transistors being characterized in that they display a conduction threshold which may be shifted to a high or low level by the application of a negative or positive WRITE voltage respectively, across the gate insulator of said transistor, said transistors being further characterized in that information may be read out of said transistor by application of an intermediate-valued READ voltage across the gate insulator, means for producing direct or inverted enabling signals in response to received WRITE or READ command signals respectively, clocked means for applying READ and WRITE sequences of voltage pulses to components in said system, means in said clocked means for applying specified gate voltages to the memory transistors in an addressed block selected in accordance with the value of a received address signal, means in said clocked means for simultaneously applying voltage pulses to the drain electrodes of all memory transistors in said array, shift register means containing m stages, each of said stages corresponding to a different one of said word columns, said stages being arranged in first and second groups so that the stages in one group correspond to alternate word columns and the stages in the other group correspond to the intermediate word columns, means for simultaneously coupling each of said stages to the source electrodes of each of the transistors in the corresponding word column in response to a STROBE pulse from said clocked means so that information may be transferred between the memory transistors in the addressed block and the corresponding stages in the shift register, each of said groups including an input stage and an output stage, said input stages including means for alternatively coupling binary input signals from a common input terminal to both input stages in response to a WRITE command signal or coupling feedback binary signals from the corresponding output stage in response to a READ command signal, said clocked means including means for producing m/2 repetitive sequences of timing pulses in an interval between STROBE pulses, each sequence including a first pair of coincident timing pulses and a second pair of delayed coincident timing pulses, said coupling means in the input stages of said first and second groups including means for enabling that coupling means in response to said first and to said delayed pairs of coincident timing pulses respectively, whereby successive binary input signals are coupled alternately to the input stages in said first and second groups, each of said register stages including means for transferring data from that stage to the succeeding stage in response to a single complete sequence of timing pulses, said READ sequence of voltage pulses including an access phase preceeding the occurrence of the repetitive sequences of timing pulses, said clocked means including means for producing a STROBE pulse and a voltage of READ magnitude to the addressed memory transistors during an access phase, whereby information stored in the addressed memory transistors is read into the shift register during said access phase, said clocked means also including means for producing positive and negative WRITE voltages successively to the addressed memory transistors and then a charging voltage to all memory transistors while said sequences of timing pulses are being applied to the shift register, whereby addressed memory transistors are prepared for the entry of fresh data, said clocked means still further including means to produce concurrent STROBE and negative WRITE pulses after the termination of said sequences of timing pulses so that information in the shift register may be transferred to the addressed memory transistors.