US3909632A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fail-safe logic circuitry for vehicle transportation control
Assignee: SASIB SpA Bologna
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Filing: 1974-03-20
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Granted: 1975-09-30
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Expires: 1994-03-20
Abstract
Abstract Logic circuitry in a vehicle transportation system, such logic circuitry providing fail-safe operation utilizing solid-state circuits. The logic circuitry is described relative to control of a highway crossing indicator, such circuitry selectively producing a most restrictive output signal or a least restrictive output signal in accordance with traffic conditions to the crossing indicator. A vital signal is generated that is characteristically differentiated from other signals in the circuit. The vital signal is serially transferred through gate circuits by corresponding enable signals to each gate circuit. When and only when the vital signal has been transferred along a path of gate circuits and through the logic circuitry, the crossing indicator assumes a least restrictive mode of operation.
Inventors
- 👤 Henry C Sibley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:50
CPC Classifications
B; B61; B61L; B61L29/00; B61L29/24; B61L29/28; B61L29/288
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
290 words
A fail-safe control circuit responsive to a first and second input control signal overlapping in duration for selectively producing a most restrictive output signal only for the duration of a first occurring signal of said first and second input control signals, comprising: a vital signal generator providing means for generating an alternating vital signal, a first and second input gate means corresponding to said first and second input control signal for gating said alternating vital signal therethrough, a first and second bistable circuit, each bistable circuit having a first signal input to set said bistable ciRcuits and a second signal input to retain said bistable circuits in a set state, the first of said first and second bistable circuits set by said alternating vital signal gated through the first of said first and second input gate means; a hold circuit connected to the second signal input of each of said first and second bistable circuits to maintain either one of said first and second bistable circuits in its previously set state when said alternating vital signal is transferred through either said first or second input gate means, a logic actuation circuit responsive to said first and second input control signals and said first and second bistable circuits to block the transfer of said alternating vital signal through said logic actuation circuit when and only when the first occurring signal of said first and second input control signals is present and its corresponding one of said first and second bistable circuits is set; a buffer circuit connected to said actuation circuit, said buffer circuit providing means for producing a least restrictive output signal when and only when said alternating vital signal is transferred to said buffer from said logic actuation circuit.
Claim 2
Dependent Claim
290 words
A fail-safe control circuit responsive to a first and second input control signal overlapping in duration for selectively producing a most restrictive output signal only for the duration of a first occurring signal of said first and second input control signals, comprising: a vital signal generator providing means for generating an alternating vital signal, a first and second input gate means corresponding to said first and second input control signal for gating said alternating vital signal therethrough, a first and second bistable circuit, each bistable circuit having a first signal input to set said bistable ciRcuits and a second signal input to retain said bistable circuits in a set state, the first of said first and second bistable circuits set by said alternating vital signal gated through the first of said first and second input gate means; a hold circuit connected to the second signal input of each of said first and second bistable circuits to maintain either one of said first and second bistable circuits in its previously set state when said alternating vital signal is transferred through either said first or second input gate means, a logic actuation circuit responsive to said first and second input control signals and said first and second bistable circuits to block the transfer of said alternating vital signal through said logic actuation circuit when and only when the first occurring signal of said first and second input control signals is present and its corresponding one of said first and second bistable circuits is set; a buffer circuit connected to said actuation circuit, said buffer circuit providing means for producing a least restrictive output signal when and only when said alternating vital signal is transferred to said buffer from said logic actuation circuit.
Claim 3
Dependent Claim
33 words
The control circuit in accordance with claim 1 wherein said alternating vital signal provided by said vital signal generator is a binary signal periodically switching between a first and a second signal level.
Claim 4
Dependent Claim
45 words
The control circuit in accordance with claim 1 wherein an inhibit circuit is connected to said first bistable circuits so that the setting of an initial one of said first and second bistable circuits inhibits the setting of the other one of said bistable circuits.
Claim 5
Dependent Claim
51 words
The control circuit in accordance with claim 1 wherein a switching circuit is included in said buffer circuit, said switching circuit having an energized state and a deenergized state and said switching circuit assuming said energized state when and only when said alternating vital signal is transferred to said buffer circuit.
Claim 6
Dependent Claim
54 words
The control circuit in accordance with claim 1 wherein said logic actuation circuit includes a plurality of serially connected solid-state gate circuits, said gate circuits providing means for serially transferring said alternating vital signal through said plurality of gate circuits in response to a separately generated enable signal to each of said gate circuits.
Claim 7
Dependent Claim
56 words
The control circuit in accordance with claim 1 wherein said first bistable circuit is set by said alternating vital signal gated through said input gate means by said first input control signal and said second bistable circuit is set by said alternating vital signal gated through said second input gate by said second input control signal.
References Cited (Backward Citations)
US3471689A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |