US3916142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of static trimming of film deposited resistors
Assignee: AG Communication Systems Corp
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Filing: 1973-03-29
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Granted: 1975-10-28
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Expires: 1993-03-29
Abstract
Abstract A method of trimming a film deposited resistor of an RC network used in a hybrid time delay circuit. After measurement of the circuit initial time delay a variable resistor is connected in parallel with the capacitor of the RC network while a voltage is applied to the time delay circuit. The variable resistance is adjusted to provide a preselected voltage drop as measured by a voltmeter. Based upon the initial and desired time delays and the value of the variable resistance to attain the first preselected voltage a final resistance value for the variable resistor is readjusted to the final value and the film resistor is trimmed until the voltage drop across the readjusted variable resistor is restored.
Inventors
- 👤 Thomas E Ennis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:55
CPC Classifications
H; H01; H01C; H01C17/00; H01C17/22; H03; H03K; H03K17/00; H03K17/28; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
235 words
A method of trimming a film deposited resistor of a resistorcapacitor combination of a time delay circuit adapted for coupling between a voltage source and a load for providing a time delay in the application of a voltage from said voltage source to said load and wherein said resistor and capacitor are coupled in series with one another and selectively in parallel with said voltage source, said method comprising the steps of selectively connecting said voltage source to said time delay circuit, measuring the time delay between connection of said voltage source to said time delay circuit and the application of said voltage to said load to thereby determine an initial time delay, selectively interconnecting a variable resistor in parallel with the capacitor of said resistor-capacitor combination, interconnecting means for measuring a voltage across said variable resistor, adjusting said variable resistor to provide a first preselected voltage thereacross, determining a final resistance value for said variable resistor according to the relationship Rf Tf/TiRi'' where Rf is said final resistance value of said variable resistor, Tf is the final time delay desired, Ti is the initial time delay measured, and Ri'' is the resistance value of said variable resistor required to attain said first preselected voltage thereacross, readjusting said variable resistor to said final resistance value, and trimming said film deposited resistor until the voltage across said variable resistor is returned to said first preselected voltage.
Claim 2
Independent Claim
235 words
A method of trimming a film deposited resistor of a resistorcapacitor combination of a time delay circuit adapted for coupling between a voltage source and a load for providing a time delay in the application of a voltage from said voltage source to said load and wherein said resistor and capacitor are coupled in series with one another and selectively in parallel with said voltage source, said method comprising the steps of selectively connecting said voltage source to said time delay circuit, measuring the time delay between connection of said voltage source to said time delay circuit and the application of said voltage to said load to thereby determine an initial time delay, selectively interconnecting a variable resistor in parallel with the capacitor of said resistor-capacitor combination, interconnecting means for measuring a voltage across said variable resistor, adjusting said variable resistor to provide a first preselected voltage thereacross, determining a final resistance value for said variable resistor according to the relationship Rf Tf/TiRi'' where Rf is said final resistance value of said variable resistor, Tf is the final time delay desired, Ti is the initial time delay measured, and Ri'' is the resistance value of said variable resistor required to attain said first preselected voltage thereacross, readjusting said variable resistor to said final resistance value, and trimming said film deposited resistor until the voltage across said variable resistor is returned to said first preselected voltage.
Claim 3
Dependent Claim
77 words
The method set forth in claim 1 wherein said time delay circuit includes a voltage activated switch coupled at one side to the connection between said resistor and said capacitor and a driver amplifier coupled between said voltage actuated switch and said load, and said step of adjusting said variable resistor to said first preselected voltage includes the selection of said first preselected voltage to be less than the voltage required to activate said voltage activated switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |