Multionomial processor system

Claim 2

A circuit for evaluating arbitrarily complex multinomial expressions comprising in combination: a plurality of multiplier-added cells, each cell having three input ports for receiving electrical signals representing, respectively, a multiplicand, a multiplier, and an addend, and an output port for producing electrical output signals representing the product of the multiplier and multiplicand which product is added to the addend; a plurality of selector means coupled to receive electrical input signals, representing variables and coefficients, for coupling the input signals to the input ports of each cell in response to control signals; and control means for applying said control signals to said selector means to produce the desired multinomial values at the output ports of said cells.

Claim 3

The invention as claimed in claim 1 wherein said input signals of said selector means includes the output signals from said cells.

Claim 4

The invention as claimed in claim 1 wherein said selector means and said control means comprise the combination of: first memory means responsive to addressing signals for coupling stored electrical signals representing multinomial coefficient values to selected input ports of said cells; second memory means responsive to addressing signals for coupling stored electrical signals representing input variables to selected input ports of said cells and for storing electrical signals from the output ports of said cells; control memory means for storing addressing signals and polynomial select signals; controller means responsive to elementary operation words for retrieving said address signals and polynomial select signals from said control memory means and for applying said address signals to said first and second memory means; and elementary operation word memory means responsive to said polynomial select signals for supplying elementary operation words to said controller means.