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US3931473A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital multiplexer system

Assignee: CSE TECHNOLOGIES Inc
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Filing: 1974-09-03
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Granted: 1976-01-06
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Expires: 1994-09-03
📄 Original PDF 🌐 Google Patents

Abstract

Abstract A second level multiplexer for a PCM data system provides for fast reframing by utilizing the stuff words in the frame organization in addition to the main framing word. This provides a clear indication of a misframe condition. In addition, integration of errors by a counter supplies immunity to medium amounts of noise. The foregoing provides for an optimum environment for frame synchronized scrambling and descrambling to be accomplished.

Inventors

  • 👤 Walton C. Ferris, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 09:57
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/0602

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 153 words
A digital multiplexer system for multiplexing a plurality of digital data channels into a serial bit stream, which is divided into frames by a frame counter means, each frame being indicated by a frame pattern for transmission to a demultiplexing receiver which also includes a frame counter means such system using a plurality of stuff words having redundant bits in said bit stream to indicate whether or not to substitute at least one stuff bit to accommodate timing irregularities, said system comprising; means for sensing said stuff words and for providing an error signal if said bits of said stuff words are not redundant because of an error during said transmission, means for sensing said frame pattern, counting means for counting said errors and providing a misframe signal, coincidence means responsive to said means for sensing said frame pattern for sensing a misframe signal for resetting said frame counter means of said receiver.
Claim 2
Dependent Claim 153 words
A digital multiplexer system for multiplexing a plurality of digital data channels into a serial bit stream, which is divided into frames by a frame counter means, each frame being indicated by a frame pattern for transmission to a demultiplexing receiver which also includes a frame counter means such system using a plurality of stuff words having redundant bits in said bit stream to indicate whether or not to substitute at least one stuff bit to accommodate timing irregularities, said system comprising; means for sensing said stuff words and for providing an error signal if said bits of said stuff words are not redundant because of an error during said transmission, means for sensing said frame pattern, counting means for counting said errors and providing a misframe signal, coincidence means responsive to said means for sensing said frame pattern for sensing a misframe signal for resetting said frame counter means of said receiver.
Claim 3
Dependent Claim 42 words
A system as in claim 1 which includes pseudo-random word generators in the transmission and receiver portions of the system for respectively scrambling and descrambling said serial bit stream the word generator in said receiver portion being reset by said coincidence means.
Claim 4
Dependent Claim 23 words
A system as in claim 1 where said counting means provides said misframe signal after a predetermined plurality of errors have been counted.
Claim 5
Dependent Claim 25 words
A system as in claim 3 where said counting means are initially reset to provide a misframe signal after only relatively few errors are received.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-01-05 1979-07-07 1980-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-01-05 1983-07-07 1984-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-01-05 1987-07-07 1988-01-06 $7700.00 Window Closed / Lapsed

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