US3934131A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output controller for initiating delayed or conditional commands via a general purpose computer
Assignee: United States Department of the Navy
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Filing: 1975-01-06
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Granted: 1976-01-20
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Expires: 1995-01-06
Abstract
Abstract The proposed command controller responds to the true or desired command d pattern and its complement which are outputted from the computer interlaced in time and checks these true-complement patterns to determine if a command format error exists. Moreover, the command pattern is checked for timing errors by comparing it against preselected minimum and maximum delay intervals corresponding to the permissible minimum and maximum time intervals for a command signal output. If the command format or its timing is incorrect, an error flag is fed back to the computer to initiate an interrupt and/or to trigger a back-up mode. The invention facilitates the use of high speed general purpose computer machines as real time, hands off, control devices for certain applications such as onboard a spacecraft or within medical electronics systems, for example.
Inventors
- 👤 James A. Perschy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
145 words
A command controller for a computer system comprising, in combination, a computer means for outputting a data signal corresponding to each desired command, comparator means responsive to said data output signal for detecting data errors within said data signal, timing error detecting means for checking said data signal corresponding to the desired command output for timing errors relative to a pair of preselected time limits corresponding respectively to minimum and maximum permitted times within said computer system for outputting of a command, said computer means further generating a signal means demarcating the desired beginning and ending time limits for said desired output command, and means responsive to said comparator means and said timing error detecting means for generating an error flag signal fed back to said computer means if a data or timing error is detected for said command output signal from said computer means.
Claim 2
Dependent Claim
145 words
A command controller for a computer system comprising, in combination, a computer means for outputting a data signal corresponding to each desired command, comparator means responsive to said data output signal for detecting data errors within said data signal, timing error detecting means for checking said data signal corresponding to the desired command output for timing errors relative to a pair of preselected time limits corresponding respectively to minimum and maximum permitted times within said computer system for outputting of a command, said computer means further generating a signal means demarcating the desired beginning and ending time limits for said desired output command, and means responsive to said comparator means and said timing error detecting means for generating an error flag signal fed back to said computer means if a data or timing error is detected for said command output signal from said computer means.
Claim 3
Dependent Claim
66 words
The combination specified in claim 1 wherein said computer means generates a command signal demarcating the intended start of a command output and wherein said timing error detecting means includes first and second multivibrator means each responsive to the start command signal generated by said computer means for respectively generating signals defining minimum and maximum time intervals during which said desired command signal should be outputted.
Claim 4
Dependent Claim
26 words
The combination specified in claim 1 wherein said error flag signal fed back to said computer means is utilized to control operation of said computer means.
Claim 5
Dependent Claim
54 words
The combination specified in claim 1 wherein said data signal comprises a pair of complementary multi-bit signals corresponding respectively to the true or desired command signal and the complement of said desired command signal, and wherein said comparator means comprises means for performing a bit-by-bit parity check between the true and complement multi-bit signals.
Claim 6
Dependent Claim
49 words
The combination specified in claim 4 wherein each data bit and its complementary bit occur in succession within said data signal and wherein said comparator means includes an exclusive OR logic circuit means operably connected to determine if in fact each data bit is followed by its complement bit.
Claim 7
Dependent Claim
34 words
The combination specified in claim 1 wherein said error flag signal producing means comprises an OR logic circuit means operably connected to said data signal error detecting means and said timing error detecting means.
References Cited (Backward Citations)
US3199077A
Cited
US3838261A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-19 | 1979-07-21 | 1980-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-19 | 1983-07-21 | 1984-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-19 | 1987-07-21 | 1988-01-20 | $7700.00 | Window Closed / Lapsed |