Semiconductor integrated circuit and method of manufacture

Claim 1

In an insulated gate semiconductor structure, a substrate bearing at least two semiconductor devices, each device including a source and a drain defining a channel therebetween, a gate insulating film overlying said channel, a polycrystalline silicon gate overlying said gate insulating film, a gate electrode connected to said gate, and stopper regions defined by impurity diffused into said substrate around each device and between said respective devices for inhibiting the formation of inversion layers in said substrate between the source and drain of each device between respective devices, the improvement comprising a stopper-diffused portion in said gate at at least one side of said gate in the channel-width direction adjacent a stopper region, said gate electrode being connected only to said stopper-free remainder of said gate, said stopper-diffused portion having impurity diffused therein of a conductivity-type corresponding to the conductivity-type of the impurity defining said stopper region and opposite in conductivity-type to at least the central region of said gate in the channel-width direction, said gate electrode being connected only to said region of said gate free of said stopper impurity, whereby a P-N junction is formed at at least said one side of said gate, and the threshold voltage necessary for producing an inversion layer under said one side of said gate is substantially greater than under the remainder of said gate.