Data detection system

Claim 2

In a data detection system to detect and locate one data item among a number of data items, the presence of each data item being revealed by the change in logic states of an access gate, the improvement characterized in that the detection and location of these data items is achieved by means forming a meshed network (Ml to Mn) having several levels in which a plurality of access gates (p) are organized in matrixes (Ml to Mn) which are in turn organized in higher groups of matrixes (G1 to G9) so as to form any number of levels, a set of counters (A, B, C) related to each of these levels to scan said access gates and thereby locate the data item at that level, and supervising element means (CR) for successively controlling the action of the counters, said counters blocked each in turn by said supervising element when a data item is detected at the corresponding level.

Claim 3

The detection system according to claim 1, wherein said means forming a meshed network comprises levels at least three in number, these levels determining respectively the order of the access gate in the matrix, the position of the matrix in its group and the number of that group and wherein the matrixes have as many inputs as access gates and a single output (Sll), common to all the access gates of the matrix.

Claim 4

The detection system according to claim 1, wherein said supervising element is a shift counter (CR) whose outputs each control the blocking of a counter, except the last output of the shift counter, which is used for indicating that a data item has been completely located.

Claim 5

The detection system according to claim 1, wherein said set of counters comprises: A first counter (A) for scanning at the first level comprising a number of outputs equal to the number of access gates per matrix, each of these outputs being connected to the input of the same order of all the matrixes; A first set of "AND" gates having two inputs (PE), equal in number to the matrixes, one input of each of these gates being connected to the output of a matrix; A second set of "AND" gates having two inputs (Q) equal in number to the number of higher groups, one input of each of these gates being controlled by the outputs of all the "AND" gates (PE) related to the matrixes of a same group; A second counter (B), with as many outputs as matrixes in a group, each of these outputs being applied to an "OR" gate (PB) and the output of each "OR" gate being connected to the second input of all the "AND" gates (PE) related to the matrixes of the same order in the different groups; A third counter (C) comprising one output per group of matrixes, each output of which is applied through an "OR" gate (PC) to the second input of the "AND" gate (Q) of the same order, the outputs of all the "AND" gates (Q) being connected to a common point (P) from which the supervising element (CR) is controlled; An inverter (I1) controlled by the first output of the supervising element (CR) and being applied to the input of all the "OR" gates (PB); and An inverter (I2) controlled by the second output of the supervising element (CR) and being applied to the inputs of all the "OR" gates (PC).

Claim 6

The detection system according to claim 1, in which the outputs of the counters (A, B, C) are connected to a logic treatment element (TL), registering the position of said counters wherein said logic treatment element is started from the last output of the supervising element (CR) and means for protection against addressing errors or detection errors.

Claim 7

The detection system according to claim 5, wherein said protection means include a clock pulse (HG) that controls the progression of a step-by-step counter (DV) whose first output is connected to the input of the counters (A, B, C), the progression of the supervising element (CR) being controlled by a monostable multivibrator (MN), to which an "AND" gate (T) one of whose inputs is connected to the common point (P) and whose other input is connected to the middle output of said step-by-step counter (DV), wherein the controlling of the supervising element (CR) is possible only once during the time between two successive control pulses of the counters (A, B AND C) and that the resetting to zero of the supervising element (CR) is controlled through an "OR" gate (OR), from three points, a normal release control pulse coming from the logic processing element (TL); a control pulse coming from the last output of the supervising element (CR) through a delay line (L) replacing the control pulse of the logic processing element (TL) if that element does not reply; a control pulse acting with a delay greater than the normal shifting time of the supervising element (CR) from the first output until the last, when the blocking of the first counter (A) from the first output of the supervising element (CR) and the absence of the data at the common point (P) are obtained simultaneously.